Spark Logic

Intel 386SX-16 connection guide

Intel 386SX-16 PQFP-100 wiring guide with power, signal assignments, and bench checks.

PQFP-100

100 contacts Current package

Intel · 100-lead plastic quad flatpack · 0.635 mm lead pitch · 25 leads per side. Use the Intel Packaging Databook outline and confirm the footprint against the fitted package.

Connect the power and ground planes

Required

Connect every VCC and VSS pin to its corresponding plane. Use distributed low-inductance bypass capacitors next to the package. This layout example shows one 100 nF ceramic per edge as a starting point. Verify transient performance and bulk decoupling for the finished board.

All 14 VCC pins and 18 VSS pins connect to planes, bypassed by four parallel 100 nF capacitors.+5 V regulatedSupply returnC1C2C3C4C1–C4: 100 nF eachVCC (14 pins)Intel 386SX-16VSS (18 pins)

Bench checks

  • Verify continuity to every VCC and VSS contact before power-up. Leave all ten NC contacts open.
  • Check 4.5–5.5 V between the planes at the CPU under load.

Intel 240187-008, §7.1. The bypass value and count shown are example layout choices.

Connection scenarios

Trace the first ROM read

Probe a populated system with decoded ROM and a READY# generator. Use 5 V-compatible high-impedance analyzer inputs and connect ground near the chipset or CPU. Trigger on RESET falling and inspect the first asserted ADS# cycle.

Bench checks

  • Expect the first fetch near 350–450 CLK2 periods after reset release when self-test is disabled.
  • The first code fetch is at physical 0xFFFFF0. At the address strobe, look for M/IO# HIGH, D/C# LOW and W/R# LOW. Check that the ROM is selected and READY# completes the cycle.
  • Probe address and data at accessible vias or buffers if required. Keep each analyzer channel on its own signal.

Intel 240187-008, §§2.8 and 5.4, Tables 5.2 and 5.6, Fig. 5.19.

PQFP-100 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

PQFP-100
Top view · index dot by pin 1 on the left edge Scroll the map to reach all contacts.
Selected pin details

17 · BLE#

Output · Control

LOW selects the lower byte lane D7–D0.

After reset · LOW during reset.

Intel 240187-008, Fig. 1.1 and Table 1.1, pp. 3–5

Electrical limits · Pin in the reference

Models and documents

Intel 5 V Intel386 SX rated at 16 MHz in the 100-lead plastic quad flatpack documented in 240187-008. The standard and low-power grades share this pinout and have different minimum clock rates. Check the fitted marking and silicon stepping before applying timing or errata.

386SX-16 Standard
4–16 MHz CPU operating range. CLK2 runs at 8–32 MHz. See Intel Table 7.7.
386SX-16 Low Power
2–16 MHz CPU operating range. CLK2 runs at 4–32 MHz. See Intel Table 7.8.