Spark Logic

Intel 386SX-16 connection guide

Intel 386SX-16 PQFP-100 wiring guide with power, signal assignments, and bench checks.

PQFP-100

100 contacts Current package

Intel · 100-lead plastic quad flatpack · 0.635 mm lead pitch · 25 leads per side. Use the Intel Packaging Databook outline and confirm the footprint against the fitted package.

Connect the power and ground planes

Required

Connect every VCC and VSS pin to its corresponding plane. Use distributed low-inductance bypass capacitors next to the package. This layout example shows one 100 nF ceramic per edge as a starting point. Verify transient performance and bulk decoupling for the finished board.

All 14 VCC pins and 18 VSS pins connect to planes, bypassed by four parallel 100 nF capacitors.+5 V regulatedSupply returnC1C2C3C4C1–C4: 100 nF eachVCC (14 pins)Intel 386SX-16VSS (18 pins)

Bench checks

  • Verify continuity to every VCC and VSS contact before power-up. Leave all ten NC contacts open.
  • Check 4.5–5.5 V between the planes at the CPU under load.

Intel 240187-008, §7.1. The bypass value and count shown are example layout choices.

Connection scenarios

Verify clock, reset and inactive inputs

Use these points to bring up an assembled system with memory and bus control. Use a 32 MHz 5 V clock driver meeting Intel’s CLK2 thresholds and edge timing. Use a 5 V reset controller synchronized to CLK2. The shown straps assume no interrupts, DMA, or address pipelining. BUSY#, ERROR#, FLT# and PEREQ have internal bias for the inactive states.

R1 20 kΩ between 5 V pull-up supply and No address pipelining5 V pull-up supplyR1 20 kΩNo address pipelining
R2 20 kΩ ±10% between 5 V pull-up supply and Address strobe inactive during hold5 V pull-up supplyR2 20 kΩ ±10%Address strobe inactive during hold
R3 20 kΩ ±10% between 5 V pull-up supply and Lock inactive during hold5 V pull-up supplyR3 20 kΩ ±10%Lock inactive during hold

Bench checks

  • Measure CLK2 with a short-ground probe close to pin 15. Check clock amplitude and edge timing against the electrical table.
  • Capture RESET at pin 33. It must stay HIGH for at least 15 stable CLK2 periods and meet setup and hold on release.

Intel 240187-008, §7.1; Intel 240187-008, §§2.8 and 5.4, Fig. 7.7; Intel 240187-008, Table 7.7.

PQFP-100 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

PQFP-100
Top view · index dot by pin 1 on the left edge Scroll the map to reach all contacts.
Selected pin details

56 · A7

Output · Address

Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.

After reset · HIGH during reset.

Intel 240187-008, Fig. 1.1 and Table 1.1, pp. 3–5

Electrical limits · Pin in the reference

Models and documents

Intel 5 V Intel386 SX rated at 16 MHz in the 100-lead plastic quad flatpack documented in 240187-008. The standard and low-power grades share this pinout and have different minimum clock rates. Check the fitted marking and silicon stepping before applying timing or errata.

386SX-16 Standard
4–16 MHz CPU operating range. CLK2 runs at 8–32 MHz. See Intel Table 7.7.
386SX-16 Low Power
2–16 MHz CPU operating range. CLK2 runs at 4–32 MHz. See Intel Table 7.8.