Intel 386SX-16 pinout

The 16 MHz Intel386 SX combines a 32-bit x86 core with a 16-bit external data bus and a 24-bit physical address space.

PQFP-100

100 contacts Current package

Intel · 100-lead plastic quad flatpack · 0.635 mm lead pitch · 25 leads per side. Use the Intel Packaging Databook outline and confirm the footprint against the fitted package.

2–16 MHz CPU operating range. CLK2 runs at 4–32 MHz. See Intel Table 7.8.

PQFP-100 pinout

PQFP-100

Top view · index dot by pin 1 on the left edge Scroll the map to reach all contacts.

Selected pin details

10 · VCC

Supply input · Power

Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.

Intel 240187-008, Fig. 1.1 and Table 1.1, pp. 3–5

Electrical limits · Link to this pin

All 100 pins

Pin	Signal	Direction	Function
1	D0 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
2	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
3	HLDA Output	Output	Bus hold acknowledge. Wait for HIGH before another master drives shared bus lines.
4	HOLD Input	Input	Active-high bus hold request. Tie LOW when no other bus master is present.
5	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
6	NA# Input	Input	Active-low request to present the next address early. Pull HIGH through about 20 kΩ if address pipelining is unused.
7	READY# Input	Input	LOW completes the bus cycle at the sampling edge. Keep HIGH while the selected target needs wait states.
8	VCC Supply input	Supply input	Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.
9	VCC Supply input	Supply input	Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.
10	VCC Supply input	Supply input	Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.
11	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
12	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
13	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
14	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
15	CLK2 Input	Input	Drive at twice the CPU frequency. For 16 MHz CPU operation use 32 MHz and meet the separate CMOS-level clock threshold.
16	ADS# Output	Output	LOW signals valid address and cycle definition. Intel recommends a 20 kΩ ±10% pull-up during bus hold.
17	BLE# Output	Output	LOW selects the lower byte lane D7–D0.
18	A1 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
19	BHE# Output	Output	LOW selects the upper byte lane D15–D8.
20	NC No connection	No connection	Leave this pin electrically open.
21	VCC Supply input	Supply input	Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.
22	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
23	M/IO# Output	Output	HIGH indicates a memory cycle, LOW indicates an I/O cycle. Decode with D/C# and W/R#.
24	D/C# Output	Output	HIGH indicates a data cycle, LOW a control cycle such as code fetch or interrupt acknowledge.
25	W/R# Output	Output	HIGH indicates write direction, LOW indicates read direction, with cycle type qualified by the other status lines.
26	LOCK# Output	Output	LOW indicates a locked bus sequence. Intel recommends a 20 kΩ ±10% pull-up during bus hold.
27	NC No connection	No connection	Leave this pin electrically open.
28	FLT# Input	Input	LOW floats outputs for in-circuit emulation. Internal pull-up keeps this inactive if unused. Follow the reset sequence in §5.4 before releasing float.
29	NC No connection	No connection	Leave this pin electrically open.
30	NC No connection	No connection	Leave this pin electrically open.
31	NC No connection	No connection	Leave this pin electrically open.
32	VCC Supply input	Supply input	Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.
33	RESET Input	Input	Active-high synchronous reset. Assert for at least 15 CLK2 periods for ordinary reset and meet setup and hold at release.
34	BUSY# Input	Input	Active-low coprocessor busy. Internal pull-up. LOW at reset release requests CPU self-test.
35	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
36	ERROR# Input	Input	Active-low coprocessor numeric error. Internal pull-up.
37	PEREQ Input	Input	Active-high coprocessor data transfer request. Internal pull-down.
38	NMI Input	Input	Rising-edge non-maskable interrupt request. Tie LOW if unused.
39	VCC Supply input	Supply input	Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.
40	INTR Input	Input	Active-high maskable interrupt request. Tie LOW if unused. The second acknowledge cycle reads the vector on D7–D0.
41	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
42	VCC Supply input	Supply input	Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.
43	NC No connection	No connection	Leave this pin electrically open.
44	NC No connection	No connection	Leave this pin electrically open.
45	NC No connection	No connection	Leave this pin electrically open.
46	NC No connection	No connection	Leave this pin electrically open.
47	NC No connection	No connection	Leave this pin electrically open.
48	VCC Supply input	Supply input	Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.
49	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
50	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
51	A2 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
52	A3 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
53	A4 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
54	A5 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
55	A6 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
56	A7 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
57	VCC Supply input	Supply input	Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.
58	A8 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
59	A9 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
60	A10 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
61	A11 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
62	A12 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
63	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
64	A13 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
65	A14 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
66	A15 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
67	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
68	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
69	VCC Supply input	Supply input	Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.
70	A16 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
71	VCC Supply input	Supply input	Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.
72	A17 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
73	A18 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
74	A19 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
75	A20 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
76	A21 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
77	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
78	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
79	A22 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
80	A23 Output	Output	Physical address bit. Decode with BLE# and BHE# to select byte lanes. Tri-states when the CPU releases the local bus.
81	D15 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
82	D14 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
83	D13 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
84	VCC Supply input	Supply input	Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.
85	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
86	D12 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
87	D11 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
88	D10 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
89	D9 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
90	D8 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
91	VCC Supply input	Supply input	Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.
92	D7 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
93	D6 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
94	D5 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
95	D4 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
96	D3 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
97	VCC Supply input	Supply input	Connect all 14 VCC pins to the regulated 5 V plane. Place multiple low-inductance bypass capacitors near the device.
98	VSS Supply return	Supply return	Connect all 18 VSS pins to the ground plane. This is the reference for power and signals.
99	D2 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.
100	D1 Bidirectional	Bidirectional	Local data bus bit. The CPU drives it on writes and samples it on reads.

Signal assignments

Local address and data bus

Decode address and status into external ROM, RAM and I/O selects. A23–A1 identify the word location. BLE# selects D7–D0 and BHE# selects D15–D8.

The CPU uses READY# for cycle completion and NA# for optional address pipelining.

Clock and reset

Drive CLK2 at twice the CPU rate and release the active-high RESET in sync with CLK2. Hold BUSY# inactive at reset release for ordinary startup. The CPU begins fetching at physical 0xFFFFF0 after internal initialization.

Bus arbitration

An external master requests the bus with HOLD and waits for HLDA before driving it. Honor LOCK# for locked sequences. FLT# is a separate in-circuit emulation input.

Interrupts

INTR is maskable. An external controller supplies the vector on D7–D0 during the second acknowledge cycle. A rising edge on NMI uses the fixed non-maskable vector.

Intel387 SX interface

A compatible Intel387 SX uses the shared bus and the dedicated busy, error and request lines. A23 HIGH with M/IO# LOW qualifies automatic coprocessor cycles. See Intel §5.7 for full interfacing.

Electrical limits

Parameter	Limit	Conditions and source
CLK2 operating range4–32 MHz	4–32 MHz	Low-power grade. Corresponds to 2–16 MHz internal CPU frequency. Intel 240187-008, Table 7.8
VCC operating range4.5–5.5 V	4.5–5.5 V	5 V ±10%, with case temperature from 0 to 100 °C. Measure with respect to the VSS plane. Intel 240187-008, Tables 7.3 and 7.4
16 MHz supply current150 mA typical · 220 mA maximum	150 mA typical · 220 mA maximum	At 32 MHz CLK2. The maximum is specified with 50 pF output loading at worst-case frequency, supply voltage and case temperature. Intel 240187-008, Tables 7.3 and 7.4
Logic input LOW / HIGH≤ 0.8 V / ≥ 2.0 V	≤ 0.8 V / ≥ 2.0 V	Normal signal inputs. CLK2 has a separate HIGH threshold. Intel 240187-008, Tables 7.3 and 7.4
CLK2 input LOW / HIGH≤ 0.8 V / ≥ VCC − 0.8 V	≤ 0.8 V / ≥ VCC − 0.8 V	At nominal VCC = 5 V, HIGH must reach at least 4.2 V. A 3.3 V oscillator cannot drive it directly. Intel 240187-008, Tables 7.3 and 7.4
CLK2 frequency and edges32 MHz at rated speed · 8 ns maximum rise and fall	32 MHz at rated speed · 8 ns maximum rise and fall	Use the 16 MHz speed column. Edge timing is measured between 0.8 V and VCC − 0.8 V. See pulse widths and load in the AC table. Intel 240187-008, Table 7.7; Fig. 7.3
RESET assertion≥ 15 CLK2 periods	≥ 15 CLK2 periods	Ordinary reset. At least 80 periods before releasing RESET with BUSY# low to request self-test. At 16 MHz CPU speed use at least 13 ns setup and 4 ns hold for synchronous release. Intel 240187-008, §§2.8 and 5.4, Fig. 7.7; Intel 240187-008, Table 7.7
Absolute maximum rail−0.5 to +6.5 V	−0.5 to +6.5 V	Stress range for VCC relative to VSS. The specified operating range is 4.5–5.5 V. Intel 240187-008, Table 7.2

Models and documents

Intel 5 V Intel386 SX rated at 16 MHz in the 100-lead plastic quad flatpack documented in 240187-008. The standard and low-power grades share this pinout and have different minimum clock rates. Check the fitted marking and silicon stepping before applying timing or errata.

386SX-16 Standard: 4–16 MHz CPU operating range. CLK2 runs at 8–32 MHz. See Intel Table 7.7.
386SX-16 Low Power: 2–16 MHz CPU operating range. CLK2 runs at 4–32 MHz. See Intel Table 7.8.

Intel386 SX Microprocessor datasheet· Intel 240187-008 · January 1994 title date · Fig. 1.1 and Table 1.1, reset, bus timing and power design · archived manufacturer document.
Intel Packaging Databook· 1999 · Chapter 2, plastic quad flatpack outline and 100-lead dimensions.
Intel 386SX-16 source register· Datasheet revision, archive provenance and file checksum.