7474 dual D flip-flop connection guide

7474 dual D flip-flop PDIP-14 wiring guide with power, signal assignments, and bench checks.

PDIP-14

14 contacts Current package

SOIC-14 14 contacts

Texas Instruments · TI package N · 2.54 mm lead pitch · SDLS119 p. 1 and packaging addendum.

Power and bypass

Required

Wire the regulated supply and its return with power off. Fit a 100 nF ceramic capacitor close to the package. Complete the chosen signal circuit before turning on power.

Regulated +5 V
- Supply +
- VCC (14)
- C1.1
Ground
- Supply return
- GND (7)
- C1.2

Bench checks

Verify 4.75–5.25 V from pin 14 to pin 7. Use the same ground for the driver and probe.

TI SDLS119, March 1988 revision, pp. 1 and 4. C1 is a local decoupling design choice.

Connection scenarios

Capture D on a clock edge

Drive the three inputs with 0–5 V outputs that can sink the specified TTL LOW input current. Pulse 1CLR# LOW then HIGH with CLK held LOW. Change D between clock edges, keeping it stable around each rising edge. Leave 2Q and 2Q# open.

Hold inactive HIGH
- Regulated +5 V
- 1PRE# (4)
- 2PRE# (10)
- 2CLR# (13)
Common ground
- GND (7)
- Driver GND
- 2D (12)
- 2CLK (11)
Initialize LOW
- TTL driver OUT A
- 1CLR# (1)
Rising-edge clock
- TTL driver OUT B
- 1CLK (3)
Observe Q
- 1Q (5)
- High-impedance probe A
Observe Q#
- 1Q# (6)
- High-impedance probe B
Data
- TTL driver OUT C
- 1D (2)

Bench checks

After clear, check Q is LOW and Q# is HIGH.
Clock in D = HIGH and then D = LOW. Q follows only on a rising edge. Allow propagation time before reading either output.

TI SDLS119, March 1988 revision, pp. 1–2 and 4.

PDIP-14 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

Top view · Pin 1 at upper left · Schematic outline

Selected pin details

1 · 1CLR#

Input · Reset / preset

Asynchronous clear. LOW forces Q LOW and Q# HIGH if PRE# is HIGH.

TI SDLS119, March 1988 revision, p. 1

Electrical limits · Pin in the reference

Models and documents

Standard commercial SN7474 TTL. Use the separate datasheet columns for military SN5474, low-power Schottky SN74LS74A or Schottky SN74S74. A CMOS 74HC74 or 74HCT74 has its own electrical and timing limits.

SN7474N / SN7474N3: Historical 14-pin plastic DIP order codes. Both are listed as obsolete in the archived TI addendum.

Texas Instruments datasheet for SN7474· SDLS119 · December 1983, revised March 1988 · pp. 1–4 for standard TTL pinout, function, and limits.
Archived Texas Instruments package option addendum· Archived manufacturer document · Addendum p. 2, historical SN7474DR, SN7474N and SN7474N3.