Spark Logic

Intel 80286 connection guide

Intel 80286 PGA-68 wiring guide with power, signal assignments, and bench checks.

LCC-68 68 contacts

PGA-68

68 contacts Current package
PLCC-68 68 contacts

Intel · Ceramic pin grid array. Two staggered rings with 2.54 mm pitch. Component-side view, pin 1 near the lower-left corner. The grid labels locate contacts on this drawing. The contact buttons use Intel’s pin numbers.

10 MHz CPU, 20 MHz CLK.

Connect power and the bias capacitor

Required

Connect both VCC pins and all three VSS pins. Put one low-impedance 100 nF bypass capacitor at the CPU socket. Use a separate 47 nF ±20% capacitor rated for at least 12 V with ≤ 1 µA leakage from CAP to VSS.

C1 100 nF between +5 V and VSS+5 VC1 100 nFVSS
C2 47 nF between CAP filter and VSSCAP filterC2 47 nFVSS

Bench checks

  • With power off, check continuity from socket contacts 30 and 62 to the +5 V rail and from 9, 35 and 60 to ground.
  • With the regulated supply on, measure 4.75–5.25 V at both VCC contacts relative to VSS.
  • Confirm continuity from CAP contact 52 to the filter capacitor and from the other capacitor terminal to VSS with power off.

Intel 210760-002, pp. 3-77–3-78, Fig. 3-73

Connection scenarios

Check clock and synchronized reset

Use this check on an assembled system with an 82C284 clock generator, the power and CAP circuit, and the local bus controller. The signal paths below are for probing the installed circuit.

Bench checks

  • Connect the scope ground to VSS near the clock circuitry. With power on, expect 12, 16, 20 or 25 MHz on CLK for a 6, 8, 10 or 12.5 MHz CPU respectively.
  • Confirm a low level of at most 0.6 V and a high level of at least 3.8 V. Measure edge times from 1.0 V to 3.6 V and back. For an 8 MHz part allow at most 10 ns, and for 10 or 12.5 MHz at most 8 ns. Keep the ground return short.
  • Capture RESET and CLK at power-up. RESET remains high during the 5 ms bias startup and for at least 16 CPU cycles after it. Check its falling edge against Intel Fig. 3-38.

Intel 210760-002, pp. 3-27–3-29, Fig. 3-18; Intel 210253-018, p. 2-100; Intel 210760-002, pp. 3-41–3-43 and 3-67–3-69

PGA-68 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

1234567891011 A B C D E F G H J K L
Top view · pin 1 at lower left Scroll the map to reach all contacts.
Selected pin details

58 · NC

No connection · NC / reserved

Leave this contact electrically open.

Intel 210253-013, p. 3-2, Fig. 2; Intel 210253-013, Table 1

Electrical limits · Pin in the reference

Models and documents

Covers the four Intel commercial HMOS speed grades listed in the September 1988 datasheet and the three package maps in its Fig. 2. Intel lists the grades and packages separately. Check the fitted part’s complete marking to identify its actual combination. System ROM, RAM, and I/O are external. Intel 80C286 and second-source parts have separate electrical specifications.

80286-6
6 MHz CPU, 12 MHz CLK at rated speed. See Intel 210760-002 for 6 MHz local-bus timing examples.
80286-8
8 MHz CPU, 16 MHz CLK.
80286-10
10 MHz CPU, 20 MHz CLK.
80286-12
12.5 MHz CPU, 25 MHz CLK.
  • Intel 80286 Hardware Reference Manual· Intel 210760-002 (1987). Ch. 3 and Fig. 3-72 cover the local bus and package maps. Fig. 3-73 covers supply and CAP. Fig. 6-1 shows the 80287 interface. Archive scan SHA-256 d3ece037a200b17ef32d78a055d0d96c3e47474d755d94569b9576a9a68c6915.
  • Intel 80286 datasheet (September 1988)· Intel 210253-013. Fig. 2 on p. 3-2 shows all three packages. Table 1 describes the pins. DC conditions are on p. 3-38. Scan SHA-256 36e1a8bf70272fcadf1163a55f02fcccaaf3e3dc73b9bd5c1ee1e8cc3229db1c.
  • Intel 80286 production datasheet (September 1993)· Intel 210253-018. Printed pp. 2-99–2-100 specify DC and AC conditions for the −8, −10, and −12 grades. The document footer identifies the revision. Scan SHA-256 afb8931d14de0834f1a70c2662e8ae27022b5b1c891edfa3d85704bccbafd595.