Asynchronous UART
Fixed mapping. P3.0/RXD is input and P3.1/TXD is output. Set both P3 latch bits to 1. For mode 1 with reception enabled, set SCON = 50h and configure the baud generator before use.
Intel 8051 pinout
Pinout, electrical limits and connections for the original HMOS Intel 8051 with 4 KiB of mask ROM, 128 bytes of RAM and two 16-bit timer/counters.
DIP-40
40 contacts Current packageDIP-40 pinout
1 · P1.0
Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input.
After reset · Latch = 1. Pulled HIGH when the pin is unloaded and used as GPIO.
All 40 pins
| Pin | Signal | Direction | Function |
|---|---|---|---|
| 1 | P1.0 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. |
| 2 | P1.1 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. |
| 3 | P1.2 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. |
| 4 | P1.3 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. |
| 5 | P1.4 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. |
| 6 | P1.5 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. |
| 7 | P1.6 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. |
| 8 | P1.7 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. |
| 9 | RST Input | Input | Active-high reset (RST/VPD in the original datasheet). Hold HIGH for at least two machine cycles after the oscillator is running. A valid reset starts code at 0000h. |
| 10 | P3.0 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. RXD receives UART data in asynchronous modes and carries serial data in shift-register mode. Keep the corresponding latch bit at 1 for the alternate function. |
| 11 | P3.1 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. TXD sends UART data in asynchronous modes and supplies shift clock in mode 0. Keep the corresponding latch bit at 1 for the alternate function. |
| 12 | P3.2 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. INT0 accepts external interrupt 0 and can gate Timer 0. Keep the corresponding latch bit at 1 for the alternate function. |
| 13 | P3.3 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. INT1 accepts external interrupt 1 and can gate Timer 1. Keep the corresponding latch bit at 1 for the alternate function. |
| 14 | P3.4 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. T0 accepts external Timer 0 count pulses. Keep the corresponding latch bit at 1 for the alternate function. |
| 15 | P3.5 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. T1 accepts external Timer 1 count pulses. Keep the corresponding latch bit at 1 for the alternate function. |
| 16 | P3.6 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. /WR strobes writes to external data memory. Keep the corresponding latch bit at 1 for the alternate function. |
| 17 | P3.7 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. /RD strobes reads from external data memory. Keep the corresponding latch bit at 1 for the alternate function. |
| 18 | XTAL2 Output | Output | Oscillator-amplifier output in the crystal configuration. Intel’s later HMOS external-drive diagram uses this node as the drive input and grounds XTAL1. |
| 19 | XTAL1 Input | Input | Oscillator-amplifier input. Connect one side of the crystal and its load capacitor here for the crystal configuration. |
| 20 | VSS Reference | Reference | Circuit ground and return for the supply, clock and logic signals. |
| 21 | P2.0 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A8 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 22 | P2.1 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A9 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 23 | P2.2 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A10 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 24 | P2.3 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A11 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 25 | P2.4 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A12 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 26 | P2.5 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A13 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 27 | P2.6 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A14 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 28 | P2.7 Bidirectional | Bidirectional | Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input. Outputs A15 during external code fetches and 16-bit external data accesses. For MOVX @Ri it outputs the P2 latch value. |
| 29 | PSEN Output | Output | Active-low external program-memory read strobe. It enables instruction bytes onto Port 0 during external fetches. |
| 30 | ALE Output | Output | Address Latch Enable. It strobes the low address byte into the external latch. Intel’s family drawing shares this position with the EPROM programming input on the 8751. |
| 31 | EA Input | Input | External Access. Strap HIGH for internal mask ROM at 0000h–0FFFh or LOW for external code from 0000h. The original family drawing uses the EA/VDD label for its EPROM variant. |
| 32 | P0.7 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD7 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 33 | P0.6 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD6 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 34 | P0.5 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD5 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 35 | P0.4 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD4 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 36 | P0.3 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD3 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 37 | P0.2 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD2 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 38 | P0.1 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD1 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 39 | P0.0 Bidirectional | Bidirectional | Open-drain GPIO. Latch 1 releases the output, so add an external pull-up when a driven HIGH is required. AD0 carries the multiplexed low address bit and data bit during external memory cycles, with an internal pull-up for bus operation. |
| 40 | VCC Supply | Supply | Connect to the regulated positive supply. Place the bypass capacitor close to VCC and ground. |
Signal assignments
Synchronous serial
Fixed mapping. In serial mode 0, RXD is bidirectional shift data and TXD outputs the shift clock. Set SM0 = 0 and SM1 = 0 in SCON, and leave both P3 latch bits at 1.
External interrupts
P3.2/INT0 and P3.3/INT1 are independent active-low inputs. Keep both latch bits high. IT0 and IT1 in TCON select low-level (0) or falling-edge (1) operation. Set the respective EX bit and global EA in IE to enable the interrupt.
Timer 0 and 1 inputs
P3.4/T0 and P3.5/T1 accept external counts when the respective C/T bit in TMOD is 1. The corresponding INT pin is a separate gate input when GATE is set. Keep each used port latch bit at 1.
External program memory
P0 outputs A0–A7 and then receives D0–D7. P2 outputs A8–A15. Latch the low address with ALE and use /PSEN as the external code read strobe. Strap EA low to start at external address 0000h. The bus occupies P0 and P2 during code fetches.
External data memory
P0 carries the low address and bidirectional data. Use ALE for the low-address latch and P3.7/RD and P3.6/WR for data strobes. P2 outputs the high address for MOVX @DPTR or its latch value for MOVX @Ri.
Electrical limits
| Parameter | Limit | Conditions and source |
|---|---|---|
| Supply4.75–5.25 V | 4.75–5.25 V | Operating table at 0–70 °C, referenced to VSS. Intel MCS-51 User’s Manual (1981), pp. 6-1–6-4 |
| Oscillator frequency1.2–12 MHz | 1.2–12 MHz | Original variable-clock AC table. One machine cycle is 12 periods. Intel MCS-51 User’s Manual (1981), pp. 6-1–6-4 |
| Digital inputsLOW ≤ 0.8 V, HIGH ≥ 2.0 V | LOW ≤ 0.8 V, HIGH ≥ 2.0 V | General digital pins. XTAL1 is excluded and RST requires ≥ 3.0 V HIGH in this edition. Intel MCS-51 User’s Manual (1981), pp. 6-1–6-4 |
| Port outputs LOW≤ 0.45 V | ≤ 0.45 V | At 1.6 mA sink for P1–P3 and 3.2 mA for P0. These are VOL test currents. Intel MCS-51 User’s Manual (1981), pp. 6-1–6-4 |
| Port outputs HIGH≥ 2.4 V | ≥ 2.4 V | At 100 µA source for P1–P3, or 400 µA for ALE, PSEN and P0 in external-bus mode. P0 GPIO requires an external pull-up. Intel MCS-51 User’s Manual (1981), pp. 6-1–6-4 |
| Reset and initializationRST HIGH for ≥ 24 oscillator periods | RST HIGH for ≥ 24 oscillator periods | Start counting after the oscillator runs. PC = 0000h, P0–P3 latches = FFh. Port levels are indeterminate before a valid reset. Intel MCS-51 Family User’s Manual (1994), chapter 3, pp. 3-25–3-27 |
| Absolute pin voltage−0.5 to +7 V | −0.5 to +7 V | Stress ratings relative to VSS. Use the operating and logic limits above for design. Intel MCS-51 User’s Manual (1981), pp. 6-1–6-4 |
Models and documents
This map covers the original Intel 8051 in the documented 40-pin DIP. Intel’s 8051AH, 80C51, ROMless 8031 and EPROM 8751 have their own electrical or programming specifications. The early original-device electrical table is marked preliminary.
- Intel 8051
- Original HMOS device, DIP-40. 4 KiB factory mask ROM, 128 B RAM, 32 port pins, two 16-bit timers, five interrupt sources and a full-duplex serial port.
- Original Intel 8031/8051/8751 preliminary specification· Intel MCS-51 User’s Manual, January 1981, chapter 6, pp. 6-1–6-6. Intel scan archived by Bitsavers. SHA-256 bbd60107a107afb680fb8ff2cea8b7fc4bf08128caba92687be204dd3676e066.
- Intel MCS-51 Family User’s Manual· Intel 272383-002, February 1994, chapter 3. Port drivers, timers, serial interface, reset and HMOS oscillator. SHA-256 99a8d2b34144f47ee6ddd9110dea75b53d5982f100c402c8dcf72f21975a2365.
- ECS HC-49USX crystal specifications· ECS-110.5-18-4XEN ordering row, 11.0592 MHz, 18 pF load and 60 Ω ESR.