AD9833 waveform generator pinout

A direct digital synthesizer (DDS) with sine, triangle and square outputs on a single pin and a write-only serial control port.

MSOP-10

10 contacts Current package

Analog Devices · RM-10 mini small outline.

RM-10 pinout. B-grade operating range −40 to +105 °C.

MSOP-10 pinout

Top view. Locate the package index before counting counterclockwise from pin 1.

Selected pin details

3 · CAP/2.5V

Regulator node · Power

When VDD exceeds 2.7 V, bypass to DGND. At 2.7 V or below, connect directly to VDD.

Analog Devices AD9833 Rev. G, Table 4

Electrical limits · Link to this pin

All 10 pins

Pin	Signal	Direction	Function
1	COMP Bias node	Bias node	DAC bias bypass node. Connect the bias capacitor to VDD as shown in the evaluation-board schematic.
2	VDD Supply	Supply	Supply for the analog circuit, interface and internal regulator.
3	CAP/2.5V Regulator node	Regulator node	When VDD exceeds 2.7 V, bypass to DGND. At 2.7 V or below, connect directly to VDD.
4	DGND Return	Return	Digital return. Reference serial and reference clock inputs to this node.
5	MCLK Input	Input	Master reference clock. The programmed output frequency scales with the measured MCLK frequency.
6	SDATA Input	Input	Serial data input. Send the most significant bit first.
7	SCLK Input	Input	Serial data is sampled on falling edges.
8	FSYNC Input	Input	Drive low to frame a 16-bit serial word.
9	AGND Return	Return	Analog return and reference for the output voltage.
10	VOUT Output	Output	Analog or square-wave output with an internal 200 Ω load resistor.

Signal assignments

Write-only serial

Frame each 16-bit word with FSYNC and meet setup and hold relative to the falling SCLK edge.

Reference clock and output

Use a stable master clock and a high-impedance load. Select the output waveform in the control register.

Electrical limits

Parameter	Limit	Conditions and source
Supply2.3–5.5 V	2.3–5.5 V	CAP/2.5V wiring changes at 2.7 V. Analog Devices AD9833 Rev. G, Table 4
Master clock25 MHz maximum	25 MHz maximum	Use a logic source that meets the input thresholds at the actual supply voltage. Analog Devices AD9833 Rev. G, Tables 1–2
Frequency incrementMCLK ÷ 2²⁸	MCLK ÷ 2²⁸	About 0.093 Hz with a 25 MHz master clock. Analog Devices AD9833 Rev. G, Frequency and Phase Registers

Models and documents

The map covers the B-grade MSOP order codes in Rev. G, including the W automotive grade. Refer to Analog Devices for automotive-grade electrical limits and enhanced-product qualification.

AD9833BRMZ: RM-10 pinout. B-grade operating range −40 to +105 °C.
AD9833BRMZ-REEL: RM-10 pinout. B-grade operating range −40 to +105 °C.
AD9833BRMZ-REEL7: RM-10 pinout. B-grade operating range −40 to +105 °C.
AD9833WBRMZ-REEL: RM-10 pinout. B-grade operating range −40 to +105 °C.

Analog Devices AD9833 Rev. G· Pin functions, operating limits and register programming.
Analog Devices UG-272· Evaluation board schematic and bias capacitor.
Source register· Document revisions, applicable order codes, consulted sections and available file checksums.