Cortex-M0 processor core

Cortex-M0 implements Armv6-M in a small 32-bit core with a three-stage pipeline and AHB-Lite interface.

Core features

Feature	What to verify
Architecture	Armv6-M
Interrupts	Integrated NVIC, with up to 32 external interrupt inputs in the processor IP. The MCU vendor decides which sources reach them.
Sleep	WFI and WFE, sleep and deep sleep signals. The chip’s power controller defines which clock domains stop.
Debug	Optional hardware debug. The MCU datasheet and board schematic identify the actual debug pins.

Before bring-up

Build with the Cortex-M0 target and use startup code and a linker script for the exact MCU.
When moving firmware from Cortex-M3, audit instructions, interrupt priorities and any assumption that the vector table can be relocated.

Manufacturer documents

Arm Cortex-M0· Processor datasheet and technical documentation.
Arm Cortex-M processor comparison· Architecture, instruction-set extensions and optional debug features.
Arm Cortex-M documentation index· Technical reference manuals, programming guides and revision-specific errata.