Cortex-M0+ processor core
Cortex-M0+ implements Armv6-M with a two-stage pipeline. The processor has configurable options for single-cycle I/O and memory protection.
Core features
| Feature | What to verify |
|---|---|
| Architecture | Armv6-M |
| I/O timing | Single-cycle I/O is an integration option. Verify which MCU registers are mapped to that path before using cycle counts. |
| Memory protection | A memory protection unit is optional. Consult the exact MCU’s feature table and startup header. |
| Trace | The Micro Trace Buffer is optional. Verify the silicon implementation and its SRAM requirements before enabling it. |
Before bring-up
- Compile for Cortex-M0+ and select the startup file for the specific device, including its interrupt table.
- For low-power firmware, check the MCU clock and wake-up tables. Use the peripheral registers to configure the actual wake source.
Manufacturer documents
- Arm Cortex-M0+· Processor datasheet and technical documentation.
- Arm Cortex-M processor comparison· Architecture, instruction-set extensions and optional debug features.
- Arm Cortex-M documentation index· Technical reference manuals, programming guides and revision-specific errata.