Spark Logic

CY7C68013A EZ-USB FX2LP controller connection guide

CY7C68013A EZ-USB FX2LP controller SSOP-56 wiring guide with power, signal assignments, and bench checks.

SSOP-56

56 contacts Current package
QFN-56 57 contacts

Infineon / Cypress · 300-mil SSOP, 24 GPIOs and 16 KiB RAM.

Bring up the clock and reset

Required

Use a 3.3 V source with a controlled ramp to operating voltage of at least 200 µs. Hold RESET# low for at least 5 ms after the supply is stable. Use a 24 MHz fundamental parallel-resonant crystal with ±100 ppm frequency tolerance and the recommended load.

C6 100 nF X7R at pin 6 between 3.3 V and Ground3.3 VC6 100 nF X7R at pin 6Ground
C10 100 nF X7R at pin 10 between 3.3 V and Ground3.3 VC10 100 nF X7R at pin 10Ground
C14 10 nF at pin 14 between 3.3 V and Ground3.3 VC14 10 nF at pin 14Ground
C18 1 nF C0G at pin 18 between 3.3 V and Ground3.3 VC18 1 nF C0G at pin 18Ground
C24 100 nF X7R at pin 24 between 3.3 V and Ground3.3 VC24 100 nF X7R at pin 24Ground
C34 100 nF X7R at pin 34 between 3.3 V and Ground3.3 VC34 100 nF X7R at pin 34Ground
C39 100 nF X7R at pin 39 between 3.3 V and Ground3.3 VC39 100 nF X7R at pin 39Ground
C50 100 nF X7R at pin 50 between 3.3 V and Ground3.3 VC50 100 nF X7R at pin 50Ground
RSCL 4.7 kΩ between 3.3 V and Boot clock3.3 VRSCL 4.7 kΩBoot clock
RSDA 4.7 kΩ between 3.3 V and Boot data3.3 VRSDA 4.7 kΩBoot data
Y1 24 MHz parallel resonance between Crystal input and Crystal outputCrystal inputY1 24 MHz parallel resonanceCrystal output
CX1 12 pF C0G between Crystal input and GroundCrystal inputCX1 12 pF C0GGround
CX2 12 pF C0G between Crystal output and GroundCrystal outputCX2 12 pF C0GGround

Bench checks

  • Check 3.3 V at every supply lead, WAKEUP high, and RESERVED at ground before releasing reset.
  • Probe CLKOUT with a high-impedance scope. Expect a 12 MHz clock with the default CPU setting.

Infineon / Cypress 38-08032 Rev. AD, Figure 1, Table 11 and operating conditions; Infineon / Cypress AN15456 Rev. G, § 3. The crystal capacitors assume the layout in Figure 1.

Connection scenarios

Check USB boot without an EEPROM

On a USB-ready PCB, route D+ and D− as a 90 Ω differential pair to the USB device connector. Use the bus-powered regulator and reset architecture in AN15456 Figure 9. Feed 3.3 V from that regulator for this test and omit the boot EEPROM.

C6 100 nF X7R at pin 6 between 3.3 V and Ground3.3 VC6 100 nF X7R at pin 6Ground
C10 100 nF X7R at pin 10 between 3.3 V and Ground3.3 VC10 100 nF X7R at pin 10Ground
C14 10 nF at pin 14 between 3.3 V and Ground3.3 VC14 10 nF at pin 14Ground
C18 1 nF C0G at pin 18 between 3.3 V and Ground3.3 VC18 1 nF C0G at pin 18Ground
C24 100 nF X7R at pin 24 between 3.3 V and Ground3.3 VC24 100 nF X7R at pin 24Ground
C34 100 nF X7R at pin 34 between 3.3 V and Ground3.3 VC34 100 nF X7R at pin 34Ground
C39 100 nF X7R at pin 39 between 3.3 V and Ground3.3 VC39 100 nF X7R at pin 39Ground
C50 100 nF X7R at pin 50 between 3.3 V and Ground3.3 VC50 100 nF X7R at pin 50Ground
RSCL 4.7 kΩ between 3.3 V and Boot clock3.3 VRSCL 4.7 kΩBoot clock
RSDA 4.7 kΩ between 3.3 V and Boot data3.3 VRSDA 4.7 kΩBoot data
Y1 24 MHz parallel resonance between Crystal input and Crystal outputCrystal inputY1 24 MHz parallel resonanceCrystal output
CX1 12 pF C0G between Crystal input and GroundCrystal inputCX1 12 pF C0GGround
CX2 12 pF C0G between Crystal output and GroundCrystal outputCX2 12 pF C0GGround

Bench checks

  • Verify the controller supply remains within 3.0–3.6 V during enumeration. Keep 5 V VBUS on the regulator input side.
  • With RESET# released and SCL and SDA pulled high, the host should enumerate VID 04B4 and PID 8613 if no EEPROM responds.
  • If it fails, inspect the differential pair and the reset interval before loading firmware.

Infineon / Cypress 38-08032 Rev. AD, USB Boot Methods; Infineon / Cypress AN15456 Rev. G, USB routing and reset.

SSOP-56 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

Locate the pin 1 mark and use the top view unless the drawing specifies a different view.
Selected pin details

53 · PD1/FD9

Bidirectional · GPIO

Port D bit 1 or FIFO data bit 9, selected by interface mode.

Infineon / Cypress 38-08032 Rev. AD, Figure 9 and Table 11

Electrical limits · Pin in the reference

Models and documents

The interactive maps cover 56-pin SSOP and QFN. The 56-ball VFBGA, 100-pin TQFP and 128-pin TQFP use separate pin assignments in Figures 7–8 and 11 of the manufacturer data sheet.

CY7C68013A-56PVXC
Commercial SSOP.
CY7C68013A-56PVXCT
Commercial SSOP tape and reel.
CY7C68013A-56PVXI
Industrial SSOP.