Spark Logic

GD32F103 connection guide

GD32F103 LQFP100 wiring guide with power, signal assignments, and bench checks.

LQFP48 48 contacts
LQFP64 64 contacts

LQFP100

100 contacts Current package

GigaDevice · GD32F103Vx · 100 leads

384 KiB Flash · 64 KiB SRAM

Power and boot from Flash

Required

Use a regulated 3.3 V supply and a single ground plane. Feed VBAT from the same rail for this single-supply setup. Fit each bypass capacitor close to its corresponding contacts. Pull BOOT0 low with 10 kΩ.

4.7 µF bulk between +3.3 V digital and Digital return+3.3 V digital4.7 µF bulkDigital return
100 nF × 5, one at each VDD lead between +3.3 V digital and Digital return+3.3 V digital100 nF × 5, one at each VDD leadDigital return
1 µF in parallel with 10 nF at VDDA between +3.3 V analog and Analog return+3.3 V analog1 µF in parallel with 10 nF at VDDAAnalog return
1 µF in parallel with 10 nF at VREFP between +3.3 V analog and Analog return+3.3 V analog1 µF in parallel with 10 nF at VREFPAnalog return
100 nF between Backup supply and Digital returnBackup supply100 nFDigital return
10 kΩ between Boot strap and Digital returnBoot strap10 kΩDigital return

Bench checks

  • Verify continuity from every supply and ground lead to its intended rail before powering up.
  • Confirm that the digital and analog rails are near 3.3 V and that BOOT0 remains low through reset.

GD32F103xx datasheet Rev. 3.3, §3.3 and Fig. 4-1. The 10 kΩ strap is a bench choice.

Connection scenarios

Connect a Serial Wire Debug probe

Keep the power circuit in place. Use a probe that senses the target’s I/O voltage on VTref. Enable its SWD mode and connect the probe’s reset output if the probe supports connection under reset.

Bench checks

  • Check that VTref measures approximately 3.3 V with respect to probe ground.
  • Select the exact part in the debugger. Start at a low SWD clock rate and check that the debug port responds before programming Flash.

GD32F10x user manual Rev. 2.9, debug port pin assignment. GD32F103xx datasheet Rev. 3.3, §2.6.

LQFP100 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

LQFP100
Top view. Pin 1 is beside the corner mark. Numbers advance counterclockwise. Scroll the map to reach all contacts.
Selected pin details

32 · PA7

Bidirectional · GPIO

GPIO and SPI0_MOSI in the PA4–PA7 assignment.

GD32F103xx datasheet Rev. 3.3, Table 2-6

Electrical limits · Pin in the reference

Models and documents

Interactive maps cover LQFP48, LQFP64 and LQFP100. See Figures 2-3 and 2-7 of the datasheet for LQFP144 and QFN36. Match the suffix on the chip. Board headers and regulator connections depend on the PCB.

GD32F103V8T6
64 KiB Flash · 20 KiB SRAM
GD32F103VBT6
128 KiB Flash · 20 KiB SRAM
GD32F103VCT6
256 KiB Flash · 48 KiB SRAM
GD32F103VDT6
384 KiB Flash · 64 KiB SRAM
GD32F103VET6
512 KiB Flash · 64 KiB SRAM
GD32F103VFT6
768 KiB Flash · 96 KiB SRAM
GD32F103VGT6
1024 KiB Flash · 96 KiB SRAM
GD32F103VIT6
2048 KiB Flash · 96 KiB SRAM
GD32F103VKT6
3072 KiB Flash · 96 KiB SRAM