Spark Logic

GD32F130 connection guide

GD32F130 LQFP48 wiring guide with power, signal assignments, and bench checks.

LQFP48

48 contacts Current package

GigaDevice · GD32F130Cx · 48 leads

16 KiB Flash · 4 KiB SRAM

Power and boot from Flash

Required

Use a regulated 3.3 V supply and a single ground plane. Feed VBAT from the same rail for this single-supply setup. Fit each bypass capacitor close to its corresponding contacts. Pull BOOT0 low with 10 kΩ.

4.7 µF bulk between +3.3 V digital and Digital return+3.3 V digital4.7 µF bulkDigital return
100 nF × 2, one at each VDD lead between +3.3 V digital and Digital return+3.3 V digital100 nF × 2, one at each VDD leadDigital return
1 µF in parallel with 10 nF at VDDA between +3.3 V analog and Analog return+3.3 V analog1 µF in parallel with 10 nF at VDDAAnalog return
100 nF between Backup supply and Digital returnBackup supply100 nFDigital return
10 kΩ between Boot strap and Digital returnBoot strap10 kΩDigital return

Bench checks

  • Verify continuity from every supply and ground lead to its intended rail before powering up.
  • Confirm that the digital and analog rails are near 3.3 V and that BOOT0 remains low through reset.

GD32F130xx datasheet Rev. 4.3, §3.3 and Fig. 4-1. The 10 kΩ strap is a bench choice.

Connection scenarios

Connect a Serial Wire Debug probe

Keep the power circuit in place. Use a probe that senses the target’s I/O voltage on VTref. Enable its SWD mode and connect the probe’s reset output if the probe supports connection under reset.

Bench checks

  • Check that VTref measures approximately 3.3 V with respect to probe ground.
  • Select the exact part in the debugger. Start at a low SWD clock rate and check that the debug port responds before programming Flash.

GD32F1x0 user manual Rev. 3.8, debug port pin assignment. GD32F130xx datasheet Rev. 4.3, §2.6.

LQFP48 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

LQFP48
Top view. Pin 1 is beside the corner mark. Numbers advance counterclockwise. Scroll the map to reach all contacts.
Selected pin details

36 · PF7

Bidirectional · GPIO

General-purpose port F, bit 7. See the package table for peripheral assignments and input tolerance.

GD32F130xx datasheet Rev. 4.3, Table 2-4

Electrical limits · Pin in the reference

Models and documents

The interactive map covers GD32F130C4, C6 and C8 in LQFP48. See datasheet §2.3 for LQFP64, LQFP32, QFN32, QFN28 and TSSOP20 maps.

GD32F130C4T6
16 KiB Flash · 4 KiB SRAM
GD32F130C6T6
32 KiB Flash · 4 KiB SRAM
GD32F130C8T6
64 KiB Flash · 8 KiB SRAM