I²C bus
Use 7-bit address 0x50 + (offset >> 8), then send the low byte of the offset.
B1:B0 select one of four 256-byte blocks. The chip ignores the next higher address bit, so 0x54–0x57 mirror 0x50–0x53.
24C08 EEPROM (24LC08B) pinout
The 24LC08B is a 8-Kbit I²C EEPROM that stores 1 KiB and writes up to 16 bytes per page.
MSOP-8 pinout
1 · A0
No internal connection. Leave open. The address selection is handled in the I²C control byte.
All 8 pins
| Pin | Signal | Direction | Function |
|---|---|---|---|
| 1 | A0 Unconnected | Unconnected | No internal connection. Leave open. The address selection is handled in the I²C control byte. |
| 2 | A1 Unconnected | Unconnected | No internal connection. Leave open. The address selection is handled in the I²C control byte. |
| 3 | A2 Unconnected | Unconnected | No internal connection. Leave open. The address selection is handled in the I²C control byte. |
| 4 | VSS Reference | Reference | Supply return and signal reference. Connect to the host ground. |
| 5 | SDA Open-drain I/O | Open-drain I/O | Serial address and data. Pull up to the bus rail and let the host and EEPROM drive only LOW. |
| 6 | SCL Input | Input | Serial clock from the host. On an open-drain bus, provide a pull-up to the bus rail. |
| 7 | WP Input | Input | Tie to VCC to protect the entire array or to VSS to enable writes. Reads are available in both states. |
| 8 | VCC Supply | Supply | Regulated 2.5–5.5 V supply. Bypass locally to VSS. |
Signal assignments
Write protection
Tie to VCC to protect the entire array or to VSS to enable writes. Reads are available in both states.
Electrical limits
| Parameter | Limit | Conditions and source |
|---|---|---|
| Operating supply2.5–5.5 V | 2.5–5.5 V | Industrial (I) and extended (E) temperature ranges are listed in the device selection table. Check the exact order code. DS20001710M · p. 1 |
| I²C clock limit400 kHz | 400 kHz | Meet the AC timing, voltage and pull-up requirements. The wiring example uses 100 kHz. DS20001710M · §1, Table 1-2 |
| Input thresholdsLOW ≤ 0.3 × VCC · HIGH ≥ 0.7 × VCC | LOW ≤ 0.3 × VCC · HIGH ≥ 0.7 × VCC | Relative to VSS over the specified supply range. Use a common-voltage bus or level shifting. DS20001710M · §1, Table 1-1 |
| SDA output LOW≤ 0.40 V | ≤ 0.40 V | Tested at 3.0 mA sink current and VCC = 2.5 V. DS20001710M · §1, Table 1-1 |
| Memory and word address1 KiB · 1 address byte | 1 KiB · 1 address byte | Offsets 0x0000–0x03FF. Client and memory addressing are described in the I²C signal assignment. DS20001710M · p. 1 and §5 |
| Page write16 bytes · 5 ms maximum write cycle | 16 bytes · 5 ms maximum write cycle | Split writes at page boundaries and use acknowledge polling after STOP. Read explicitly addressed data after power-up. DS20001710M · Table 1-2 and §§6–8 |
Models and documents
This reference covers the standard package codes listed for Microchip 24LC08B in the linked datasheet. Match the full manufacturer part number before wiring a device marked 24C08. Use its own datasheet for other manufacturers or the Microchip AA and FC versions. The four-ball CSP drawing in the family datasheet applies to 24AA08.
- 24LC08B
- The /MS package suffix selects this outline. Check the ordering table for supported temperature and reel combinations.
- Microchip 24LC08B datasheet· DS20001710M · 2021-03 · Device selection and diagrams on p. 1, electrical limits in §1, pin assignments in §2 and transactions in §§5–8.
- Microchip AN1028 · Recommended usage of I²C serial EEPROMs· DS01028B · Figure 1, bus pull-ups, power-up, acknowledge polling and recovery.
- Microchip DFN-8 package drawing· C04-123 and C04-2123 Rev E · MC outline and optional center land pad.
- Source versions and checksums· Document revisions, source URLs and SHA-256 checksums for the consulted manufacturer files.