7474 dual D flip-flop connection guide

• Regulated +5 V
  • Supply +
  • VCC (14)
  • C1.1
• Ground
  • Supply return
  • GND (7)
  • C1.2

Bench checks

• Verify 4.75–5.25 V from pin 14 to pin 7. Use the same ground for the driver and probe.

TI SDLS119, March 1988 revision, pp. 1 and 4. C1 is a local decoupling design choice.

Divide a clock by two

• Hold inactive HIGH
  • Regulated +5 V
  • 1PRE# (4)
  • 2PRE# (10)
  • 2CLR# (13)
• Common ground
  • GND (7)
  • Driver GND
  • 2D (12)
  • 2CLK (11)
• Initialize LOW
  • TTL driver OUT A
  • 1CLR# (1)
• Rising-edge clock
  • TTL driver OUT B
  • 1CLK (3)
• Observe Q
  • 1Q (5)
  • High-impedance probe A
• Toggle feedback
  • 1Q# (6)
  • 1D (2)
  • High-impedance probe B

Bench checks

• Verify CLK at 1 kHz and Q at 500 Hz. Verify the feedback stays stable for at least 5 ns after CLK↑ on the fitted part. The datasheet does not guarantee a minimum clock-to-output delay for a direct feedback loop.
• The single D load draws up to 1.6 mA LOW and 40 µA HIGH, within the Q# output drive. At 5 V and 25 °C the datasheet lists up to 40 ns CLK-to-output delay with its specified test load.

TI SDLS119, March 1988 revision, pp. 1 and 4.

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

Standard commercial SN7474 TTL. Use the separate datasheet columns for military SN5474, low-power Schottky SN74LS74A or Schottky SN74S74. A CMOS 74HC74 or 74HCT74 has its own electrical and timing limits.

SN7474N / SN7474N3

Historical 14-pin plastic DIP order codes. Both are listed as obsolete in the archived TI addendum.

• Texas Instruments datasheet for SN7474· SDLS119 · December 1983, revised March 1988 · pp. 1–4 for standard TTL pinout, function, and limits.
• Archived Texas Instruments package option addendum· Archived manufacturer document · Addendum p. 2, historical SN7474DR, SN7474N and SN7474N3.