The TI SN7474 contains two independent positive-edge-triggered TTL flip-flops with complementary outputs and asynchronous preset and clear.
Data sampled on the rising CLK edge when both asynchronous controls are HIGH.
| Pin | Signal | Direction | Function |
|---|---|---|---|
| 1 | 1CLR# Input | Input | Asynchronous clear. LOW forces Q LOW and Q# HIGH if PRE# is HIGH. |
| 2 | 1D Input | Input | Data sampled on the rising CLK edge when both asynchronous controls are HIGH. |
| 3 | 1CLK Input | Input | Positive-edge clock. Meet the HIGH and LOW pulse widths and the D setup and hold times. |
| 4 | 1PRE# Input | Input | Asynchronous preset. LOW forces Q HIGH and Q# LOW if CLR# is HIGH. |
| 5 | 1Q Output | Output | Non-inverting stored output. A power-up state is unspecified until an asynchronous control or a valid clock edge sets it. |
| 6 | 1Q# Output | Output | Complementary stored output during normal operation. Both outputs are HIGH if PRE# and CLR# are both LOW. |
| 7 | GND Reference | Reference | Supply return and reference for all input and output levels. |
| 8 | 2Q# Output | Output | Complementary stored output during normal operation. Both outputs are HIGH if PRE# and CLR# are both LOW. |
| 9 | 2Q Output | Output | Non-inverting stored output. A power-up state is unspecified until an asynchronous control or a valid clock edge sets it. |
| 10 | 2PRE# Input | Input | Asynchronous preset. LOW forces Q HIGH and Q# LOW if CLR# is HIGH. |
| 11 | 2CLK Input | Input | Positive-edge clock. Meet the HIGH and LOW pulse widths and the D setup and hold times. |
| 12 | 2D Input | Input | Data sampled on the rising CLK edge when both asynchronous controls are HIGH. |
| 13 | 2CLR# Input | Input | Asynchronous clear. LOW forces Q LOW and Q# HIGH if PRE# is HIGH. |
| 14 | VCC Supply | Supply | Connect to a regulated 5 V rail. Place a local bypass capacitor to GND. |
With PRE# and CLR# HIGH, Q captures D at CLK↑ and Q# is its complement. Hold CLK steady to retain state. Either asynchronous input overrides the clock. Do not assert both at once: both outputs go HIGH and the state after simultaneous release is indeterminate.
With PRE# and CLR# HIGH, Q captures D at CLK↑ and Q# is its complement. Hold CLK steady to retain state. Either asynchronous input overrides the clock. Do not assert both at once: both outputs go HIGH and the state after simultaneous release is indeterminate.
| Parameter | Limit | Conditions and source |
|---|---|---|
| VCC operating range4.75–5.25 V | 4.75–5.25 V | Nominal 5 V; commercial free-air temperature 0–70 °C. All voltages relative to pin 7. TI SDLS119, March 1988 revision, p. 4 |
| TTL input thresholdsVIL ≤ 0.8 V · VIH ≥ 2.0 V | VIL ≤ 0.8 V · VIH ≥ 2.0 V | Use defined levels on every input, including the unused flip-flop. TI SDLS119, March 1988 revision, p. 4 |
| LOW input current1.6 mA (D, PRE#) · 3.2 mA (CLK, CLR#) | 1.6 mA (D, PRE#) · 3.2 mA (CLK, CLR#) | Magnitude per input. The driver must sink this current while meeting the LOW threshold. TI SDLS119, March 1988 revision, p. 4 |
| Output HIGHVOH ≥ 2.4 V | VOH ≥ 2.4 V | IOH = −0.4 mA and VCC = 4.75 V. Check the next receiver against this guaranteed HIGH level. TI SDLS119, March 1988 revision, p. 4 |
| Output LOWVOL ≤ 0.4 V | VOL ≤ 0.4 V | IOL = 16 mA and VCC = 4.75 V. TI SDLS119, March 1988 revision, p. 4 |
| Data setup and hold20 ns setup · 5 ns hold | 20 ns setup · 5 ns hold | Minimum times around CLK↑. TI SDLS119, March 1988 revision, p. 4 |
| Minimum pulse widths30 ns CLK HIGH · 37 ns CLK LOW · 30 ns PRE# or CLR# LOW | 30 ns CLK HIGH · 37 ns CLK LOW · 30 ns PRE# or CLR# LOW | Apply all minimum widths together. TI SDLS119, March 1988 revision, p. 4 |
| Absolute maximum7 V VCC · 5.5 V input | 7 V VCC · 5.5 V input | Stress limits, relative to GND. Operate within the recommended supply and valid logic conditions. TI SDLS119, March 1988 revision, p. 3 |
Standard commercial SN7474 TTL. Use the separate datasheet columns for military SN5474, low-power Schottky SN74LS74A or Schottky SN74S74. A CMOS 74HC74 or 74HCT74 has its own electrical and timing limits.