74AHCT595D

Nexperia · 8-bit shift register with output latches

SO16 (D)

9.90 × 3.90 mm · 1.27 mm pitch

SOT109-1 package outline

Pinout

Top view · Pin 1 at upper left · Schematic outline
Arrows show signal direction between paired pins.

DS → Q7S follows the internal eight-stage shift path.

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12 STCP

Storage clock. A rising edge copies the shift register to the storage register.

Electrical limits for this pin

All 16 pins

Pin	Signal	Function
1	Q1	Stored bit 1 for MSB-first transmission. Drives when OE is LOW and goes high impedance when OE is HIGH.
2	Q2	Stored bit 2 for MSB-first transmission. Drives when OE is LOW and goes high impedance when OE is HIGH.
3	Q3	Stored bit 3 for MSB-first transmission. Drives when OE is LOW and goes high impedance when OE is HIGH.
4	Q4	Stored bit 4 for MSB-first transmission. Drives when OE is LOW and goes high impedance when OE is HIGH.
5	Q5	Stored bit 5 for MSB-first transmission. Drives when OE is LOW and goes high impedance when OE is HIGH.
6	Q6	Stored bit 6 for MSB-first transmission. Drives when OE is LOW and goes high impedance when OE is HIGH.
7	Q7	Stored bit 7 for MSB-first transmission. Drives when OE is LOW and goes high impedance when OE is HIGH.
8	GND	Supply return and reference for all signal voltages.
9	Q7S	Serial output of the last shift stage. Remains driven when OE is HIGH.
10	MR	Active-LOW asynchronous reset. Clears the shift register and Q7S. The storage register retains its word until STCP rises.
11	SHCP	Shift clock. A rising edge samples DS and advances the previous bits one stage.
12	STCP	Storage clock. A rising edge copies the shift register to the storage register.
13	OE	Active-LOW parallel output enable. HIGH puts Q0–Q7 in high impedance and leaves both registers unchanged.
14	DS	Serial data input, sampled on the rising edge of SHCP.
15	Q0	Stored bit 0 for MSB-first transmission. Drives when OE is LOW and goes high impedance when OE is HIGH.
16	VCC	Positive supply. Place the bypass capacitor close to this pin and GND.

Rising SHCP shifts data and rising STCP copies it to the storage register. With the two clocks tied together, storage captures the pre-shift word and trails by one clock. MR clears the shift register only. Pulse STCP after clearing to copy zeros to the storage register.

AHCT electrical limits

Recommended VCC is 4.5–5.5 V at −40 to +125 °C. Voltages are referenced to GND. Recommended input voltage is 0–5.5 V and output voltage is 0 V to VCC. The inputs have Schmitt-trigger action and TTL-compatible thresholds.

AHCT digital input thresholds

For all digital inputs over the recommended VCC range, LOW is ≤ 0.8 V and HIGH is ≥ 2.0 V. The maximum input transition time per volt is 20 ns/V. Check the host’s guaranteed output levels under its actual load. A 3.3 V signal can meet these thresholds while the 74AHCT595D runs from a 5 V supply.

AHCT output levels at 4.5 V

Load magnitude	VOL max	VOH min
50 µA	0.10 V	4.40 V
8 mA	0.55 V	3.70 V

Limits apply at −40 to +125 °C with a valid input and the measured output driven. IOH is negative (source) and IOL is positive (sink). These are output-voltage test loads. Nexperia lists ±25 mA per output and 75 mA magnitude through VCC or GND as absolute stress limits. Check receiver voltage tolerance, including on Q7S.

AHCT clock and data timing

Event	Limit
SHCP or STCP HIGH or LOW, MR LOW	5 ns min
DS setup before SHCP ↑	3 ns min
DS hold after SHCP ↑	2 ns min
SHCP ↑ to STCP ↑	5 ns min
MR release to SHCP ↑	3 ns min
SHCP to Q7S propagation at 50 pF	12 ns max

Limits at 4.5–5.5 V over −40 to +125 °C. With a shared shift clock, the 1 ns minimum clock-to-Q7S delay alone cannot cover the 2 ns DS hold requirement. Lower clock frequency does not resolve this hold constraint. The bench cascade uses separate, staggered shift clocks.

Source: Nexperia 74AHC_AHCT595 Rev. 9, §§ 8–11, Tables 4–7 (AHCT rows).

Ordering and documents

Nexperia lists the active order code below (12NC 935265559118). Package marking is 74AHCT595D.

74AHCT595D,118

SO16 pin map: § 6.1 (D package) and Table 2. Function and waveforms: Table 3 and Figures 6–11. Mechanical outline: Figure 12.