74HC14 connection guide
Wire a TI SN74HC14 to invert a logic signal or convert a slow edge to a digital transition.
Connect and bypass the supply
With power off, connect a regulated 4.5 V supply to 14 VCC and its return to 7 GND. Fit C1, a 100 nF ceramic capacitor rated at least 16 V, directly across these pins with short leads. Connect the logic source and meter grounds to the same return.
Finish the logic wiring below before powering up. Verify 4.5 V at pin 14 with the meter common at pin 7.
Choose a signal circuit
Connect a source that swings from 0 V to VCC directly to 1A (pin 1). Use a single gate when you need the opposite logic level or need to reverse the active clock edge. TI Figure 8-1 shows the clock example. Read the result at 1Y (pin 2).
Tie unused inputs 3, 5, 9, 11, 13 to pin 7 and leave their outputs open. Keep the source within the IC’s rails and enable it only while the IC is powered.
Arrows show signal direction between paired pins.
Check both logic states
| Source voltage | Output (pin 2) |
|---|---|
| LOW (0 V) | HIGH |
| HIGH (VCC) | LOW |
Measure the settled output relative to pin 7 with a high-impedance meter. At 4.5 V and a load of 20 µA or less, expect LOW ≤ 0.1 V and HIGH ≥ 4.4 V. If either state is wrong, check pin 14, pin 1 and any jumper at the package before checking the output.
Package and documents
TI package code NS · 10.3 × 5.3 mm nominal body · 1.27 mm lead pitch. Use TI’s package outline for footprint dimensions and tolerances.
TI lists these active order codes in its 18 September 2026 addendum. SN74HC14NSR, SN74HC14NSR.A, SN74HC14NSRE4.
- TI NS package drawing (PDF)
- TI SNx4HC14 datasheet (PDF)· SCLS085L, Rev. L (February 2025), with package option addendum
- TI SN74HC14 product and ordering information
- TI Understanding Schmitt Triggers· SCEA046B, Rev. B (April 2025). Slow edges, noise, hysteresis and switch filtering.
TI SCLS085L §§ 7.3 and 8 explain input behavior, clock polarity, bypassing and unused pins.