Spark Logic

74HC165 connection guide

Wire and test a Texas Instruments SN74HC165 for parallel capture, serial readout or a two-chip chain.

Connect and bypass the supply

With power off, connect the regulated 4.5 V rail to 16 VCC and the supply return to 8 GND. Use a common ground for the host, the register and the test instrument. Fit one 100 nF ceramic capacitor directly across pins 16 and 8 of each chip, close to the package.

4.5 V to pin 16, return to pin 8, 100 nF across both pins on each chip4.5 VReturn100 nF16 VCC8 GND

Complete the signal wiring before power-up. Then measure 4.5 V at pin 16 with the meter common at pin 8. Keep the host outputs from driving the chip while its supply is off.

1 SH/LD 2 CLK 3 E 4 F 5 G 6 H 7 Q̅H 8 GND Used in this circuit
16 VCC Used in this circuit15 CLK INH 14 D 13 C 12 B 11 A 10 SER 9 QH
Top view · Pin 1 at upper left · Schematic outline

Connect the data and control signals

Read one register

Jump to the expected result ↓

Use fast CMOS host outputs that swing between GND and the same 4.5 V rail. The receiver on 9 QH must accept that swing. Leave 7 Q̅H open. VCC and GND labels in the signal schematic refer to the same rails as in the power step.

Host LOAD to pin 1 and CLK to pin 2. Pins 10 and 15 to ground. Pin 9 to host input. A through H tied to the example levels in the wiring table.U1 · 74HC165Host LOAD1 SH/LDHost CLK2 CLKGND15 CLK INHVCC11 AGND12 BVCC13 CVCC14 DGND3 EVCC4 FGND5 GGND6 H10 SER9 QHGNDHost IN
1 SH/LD Used in this circuit2 CLK Used in this circuit3 E 4 F 5 G 6 H 7 Q̅H 8 GND
16 VCC 15 CLK INH Used in this circuit14 D 13 C 12 B 11 A 10 SER Used in this circuit9 QH Used in this circuit
Top view · Pin 1 at upper left · Schematic outline

Each rising 2 CLK advances the word toward 9 QH and admits the next 10 SER bit.

Signal wiring for the test pattern

PinConnect to
1 SH/LDHost LOAD
2 CLKHost CLK
15 CLK INHGND
10 SERGND for zero fill
9 QHHost input
11 A,13 C,14 D,4 FU1 to VCC
12 B,3 E,5 G,6 HU1 to GND

Check the result

  1. Keep 2 CLK LOW and CLK INH grounded. With A–H stable, drive 1 SH/LD LOW for at least 1 µs, then HIGH. Keep the data stable throughout the LOW interval.
  2. Wait at least 1 µs after releasing LOAD. Sample QH first with CLK LOW, then drive CLK HIGH for at least 1 µs and back LOW. Allow at least 1 µs in the LOW phase. Repeat sample-before-pulse until you have eight samples. You can skip the last pulse.
  3. Probe QH and CLK relative to pin 8. Expect 00101101 from left to right. The order is H → G → F → E → D → C → B → A, followed by zeros if you keep shifting.

At 4.5 V TI specifies a settled LOW of at most 0.1 V at 20 µA sink current and a settled HIGH of at least 4.4 V at 20 µA source current. If the sequence is offset by one bit, check the first sample relative to CLK. If you drive CLK INH in another design, raise it only while CLK is HIGH. Raising it while CLK is LOW in shift mode can clock an extra bit.

Timing limits and input thresholds

Package and documents

TI package code PW · approximately 5 × 4.4 mm body · 0.65 mm lead pitch. Use the outline drawing for footprint dimensions and tolerances.

Active order codes
SN74HC165PWR, SN74HC165PWR.A, SN74HC165PWRG3, SN74HC165PWRG3.A, SN74HC165PWRG4, SN74HC165PWRG4.A
Obsolete
SN74HC165PW, SN74HC165PWT

Package status is from TI's 23 October 2026 addendum, pp. 1–2. Circuit sources: §§5, 6.3, 6.7, 6.10, 6.13, 8.2–8.4, 9.2 Figure 5 and 10.