74HC595 shift register
TI SN74HC595 SSOP-16 pinout, input thresholds, output drive, clock timing and ordering codes.
Pinout
16 · VCC
Positive supply · 2–6 V
Connect a regulated supply and place a 100 nF ceramic capacitor across VCC and GND at the package.
All 16 pins
| Pin | Signal | Role | Range |
|---|---|---|---|
| 1 | QB | Latched parallel output, bit 1 | 0 V to VCC |
| 2 | QC | Latched parallel output, bit 2 | 0 V to VCC |
| 3 | QD | Latched parallel output, bit 3 | 0 V to VCC |
| 4 | QE | Latched parallel output, bit 4 | 0 V to VCC |
| 5 | QF | Latched parallel output, bit 5 | 0 V to VCC |
| 6 | QG | Latched parallel output, bit 6 | 0 V to VCC |
| 7 | QH | Latched parallel output, bit 7 | 0 V to VCC |
| 8 | GND | Supply return and signal reference | 0 V |
| 9 | QH′ | Serial cascade output | 0 V to VCC |
| 10 | /SRCLR | Active-LOW shift-register clear | 0 V to VCC |
| 11 | SRCLK | Shift clock | 0 V to VCC |
| 12 | RCLK | Storage-register clock | 0 V to VCC |
| 13 | /OE | Active-LOW parallel output enable | 0 V to VCC |
| 14 | SER | Serial data input | 0 V to VCC |
| 15 | QA | Latched parallel output, bit 0 | 0 V to VCC |
| 16 | VCC | Positive supply | 2–6 V |
QH′ is the serial output of the shift register. QH is bit 7 of the separate storage register. The prime identifies the serial tap.
Pin assignments are from TI SCLS041J §5 top view and Figure 9-1. The drawings identify pin 16 as VCC.
Electrical limits
Operate the SN74HC595 at VCC 2–6 V and free-air temperature −40 to +85 °C. Voltages are relative to GND. Drive inputs between GND and VCC with fast edges and terminate every unused input. The maximum input transition time at 4.5 V is 500 ns (§6.3).
Digital input thresholds
| VCC | VIL max (LOW) | VIH min (HIGH) |
|---|---|---|
| 2 V | 0.5 V | 1.5 V |
| 4.5 V | 1.35 V | 3.15 V |
| 6 V | 1.8 V | 4.2 V |
Driven output levels
| Supply · outputs · load | VOL max | VOH min |
|---|---|---|
| 4.5 V · all outputs · ±20 µA | 0.1 V | 4.4 V |
| 4.5 V · QA–QH · ±6 mA | 0.33 V | 3.84 V |
| 4.5 V · QH′ · ±4 mA | 0.33 V | 3.84 V |
| 6 V · QA–QH · ±7.8 mA | 0.33 V | 5.34 V |
| 6 V · QH′ · ±5.2 mA | 0.33 V | 5.34 V |
These limits apply over −40 to +85 °C with valid input levels, using positive IOL for sinking and negative IOH for sourcing (§6.5). At 4.5 V the ±6 mA QA–QH test point describes individual output levels. Check combined supply and return currents, output voltage drop, switching current and thermal dissipation for simultaneous loads. Use an external driver for loads beyond the logic outputs’ capabilities.
Absolute stress limits are ±35 mA per output and ±70 mA through VCC or GND (§6.1). Design to the operating conditions in §6.3 and guaranteed levels in §6.5.
Clock and clear timing at 4.5 V
| Interval | Minimum (−40 to +85 °C) |
|---|---|
| SER setup before SRCLK ↑ | 25 ns |
| SER hold after SRCLK ↑ | 0 ns |
| SRCLK ↑ to RCLK ↑ | 19 ns |
| SRCLK or RCLK HIGH or LOW | 20 ns |
| /SRCLR LOW pulse | 20 ns |
| /SRCLR LOW before RCLK ↑ | 13 ns |
| /SRCLR HIGH before SRCLK ↑ | 12 ns |
At 4.5 V with 50 pF load, maximum SRCLK → QH′ delay is 40 ns and maximum RCLK → QA–QH delay is 37 ns. /OE takes up to 50 ns to disconnect QA–QH and up to 37 ns to enable them. If sharing a bus, leave time for one driver to disconnect before enabling another. See SCLS041J §§6.6–6.7 and Figure 6-1.
Compare HC595 and HCT595 input levels
| Parameter | SN74HC595 | SN74HCT595 |
|---|---|---|
| Operating VCC | 2–6 V | 4.5–5.5 V |
| VIL max at 4.5 V | 1.35 V | 0.8 V |
| VIH min at 4.5 V | 3.15 V | 2.0 V |
| Free-air temperature | −40 to +85 °C | −40 to +125 °C |
HCT uses TTL-compatible thresholds of 0.8 V and 2.0 V across its supply range. For HC, TI’s interpolation method gives approximately 1.50 V and 3.50 V at 5 V. A 3.3 V controller can meet the 5 V HCT input thresholds if its guaranteed LOW and HIGH levels meet those limits under load. For HC at 5 V use a compatible driver or level translator. Check the receiving pin’s voltage limits if sending signals back to the 3.3 V domain.
Both TI datasheets list VOL ≤0.33 V and VOH ≥3.84 V at 4.5 V and ±6 mA across their respective temperature ranges. The HC table applies this load to QA–QH and specifies QH′ separately at ±4 mA. Compare TI SCLS041J and SCLS880A §§6.3 and 6.5, and TI’s threshold interpolation example.
Package and documents
TI package code DB · 6.2 × 5.3 mm nominal body · 0.65 mm lead pitch. See the TI package drawing for footprint dimensions and tolerances.
Catalog SN74HC595 ordering suffixes for this package in the TI 18 September 2026 addendum. Active: DBR, DBR.A, DBRE4, DBRG4.
- TI SNx4HC595 datasheet (PDF)· SCLS041J, October 2021, with package option addendum
- TI SN74HC595 product and ordering information
- TI SN74HCT595 datasheet (PDF)· SCLS880A, December 2021
Related TI lines have separate documentation, including the SN74HC595B in X1QFN and SN74HC595-EP. The SN54HC595 military pinouts are in §5 of SCLS041J.