74HCT595
TI · 8-bit shift register with output latches
TSSOP-16 (PW)
5.00 × 4.40 mm · 0.65 mm pitchPinout
Arrows show signal direction between paired pins.
SER → QH′ follows the internal eight-stage shift path.
Go to selected pin details ↓15 QA
Stored bit 0 for MSB-first transmission. Drives when /OE is LOW and goes high impedance when /OE is HIGH.
Electrical limits for this pinAll 16 pins
| Pin | Signal | Function |
|---|---|---|
| 1 | QB | Stored bit 1 for MSB-first transmission. Drives when /OE is LOW and goes high impedance when /OE is HIGH. |
| 2 | QC | Stored bit 2 for MSB-first transmission. Drives when /OE is LOW and goes high impedance when /OE is HIGH. |
| 3 | QD | Stored bit 3 for MSB-first transmission. Drives when /OE is LOW and goes high impedance when /OE is HIGH. |
| 4 | QE | Stored bit 4 for MSB-first transmission. Drives when /OE is LOW and goes high impedance when /OE is HIGH. |
| 5 | QF | Stored bit 5 for MSB-first transmission. Drives when /OE is LOW and goes high impedance when /OE is HIGH. |
| 6 | QG | Stored bit 6 for MSB-first transmission. Drives when /OE is LOW and goes high impedance when /OE is HIGH. |
| 7 | QH | Stored bit 7 for MSB-first transmission. Drives when /OE is LOW and goes high impedance when /OE is HIGH. |
| 8 | GND | Supply return and reference for all signal voltages. |
| 9 | QH′ | Serial output of the last shift stage. Remains driven when /OE is HIGH. |
| 10 | /SRCLR | Active-LOW asynchronous shift-register clear. The stored outputs retain their previous word until RCLK rises. |
| 11 | SRCLK | Shift-register clock. Each rising edge loads SER and advances the existing bits one position. |
| 12 | RCLK | Storage-register clock. A rising edge copies the shift register to the parallel output register. |
| 13 | /OE | Active-LOW parallel output enable. HIGH puts QA–QH in high impedance while both registers retain their data. |
| 14 | SER | Serial data input, sampled on the rising edge of SRCLK. |
| 15 | QA | Stored bit 0 for MSB-first transmission. Drives when /OE is LOW and goes high impedance when /OE is HIGH. |
| 16 | VCC | Positive supply. Place the bypass capacitor close to this pin and GND. |
Rising SRCLK shifts data and rising RCLK copies it to the storage register. With the two clocks tied together, storage captures the pre-shift word and trails by one clock. /SRCLR clears the shift register only. Pulse RCLK after clearing to copy zeros to the storage register.
HCT electrical limits
Recommended VCC is 4.5–5.5 V at −40 to +125 °C. Voltages are referenced to GND. Inputs and outputs operate within 0 V to VCC. The clamps can conduct outside the rails.
HCT digital input thresholds
For all digital inputs over the recommended VCC range, LOW is ≤ 0.8 V and HIGH is ≥ 2.0 V. The maximum input transition time per volt is 500 ns/V. Check the host’s guaranteed output levels under its actual load. A 3.3 V signal can meet these thresholds while the SN74HCT595 runs from a 5 V supply.
HCT output levels at 4.5 V
| Load magnitude | VOL max | VOH min |
|---|---|---|
| 20 µA | 0.10 V | 4.40 V |
| 6 mA | 0.33 V | 3.84 V |
Limits apply at −40 to +125 °C with a valid input and the measured output driven. IOH is negative (source) and IOL is positive (sink). These are output-voltage test loads. TI lists ±35 mA per output and ±70 mA through VCC or GND as absolute stress limits. Check receiver voltage tolerance, including on QH′.
HCT clock and data timing
| Event | Limit |
|---|---|
| SRCLK or RCLK HIGH or LOW, /SRCLR LOW | 20 ns min |
| SER setup before SRCLK ↑ | 25 ns min |
| SER hold after SRCLK ↑ | 0 ns min |
| SRCLK ↑ to RCLK ↑ | 20 ns min |
| /SRCLR release to SRCLK ↑ | 12 ns min |
| SRCLK to QH′ propagation | 53 ns max |
Limits at 4.5–5.5 V over −40 to +125 °C. For a shared-clock cascade, budget the 53 ns clock-to-QH′ delay, 25 ns SER setup, clock skew and margin. TI measures the 25 MHz single-device figure at 4.5 V under its switching test conditions.
Source: TI SCLS880A Rev. A, §§ 6.1, 6.3, 6.5–6.7 and 8.2–8.3.
Ordering and documents
TI’s package addendum lists both codes in PW with 2,000 parts per reel.
SN74HCT595PWRSN74HCT595PWR.A
- TI SN74HCT595 datasheet· SCLS880A · Rev. A · December 2021
- TI SN74HCT595 product and ordering information
- TI PW0016A package outline· 4220204/B · December 2023
- TI SN74HCT595PWR ordering codes
Pin map: Figure 5-1 and Table 5-1. Circuit references: §§ 8–11. Ordering: package option addendum. TI documents the separately qualified SN74HCT595-Q1 on its automotive product page.