Identification I²C
The CPU card uses the chassis identification EEPROM before enabling other interfaces.
EOMA68 CPU card interface pinout
EOMA68 defines a 68-contact connection between a CPU card and a compatible chassis. The v1.0 assignment includes LCD, I²C, USB, Ethernet and multiplexed GPIO.
EOMA68 v1.0 connector
68 contacts Current packageEOMA68 v1.0 connector pinout
1 · SPI_MISO / GPIO12
Check the chassis and CPU card implementation for interface support and multiplexing.
All 68 pins
| Pin | Signal | Direction | Function |
|---|---|---|---|
| 1 | SPI_MISO / GPIO12 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 2 | B2 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 3 | B4 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 4 | B6 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 5 | SPI_SCK / GPIO14 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 6 | G2 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 7 | G4 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 8 | G6 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 9 | EINT1 / GPIO16 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 10 | R2 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 11 | R4 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 12 | R6 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 13 | LCD_PCLK Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 14 | LCD_HSYNC Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 15 | I²C_SCL Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 16 | SD_D3 / GPIO0 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 17 | GPIO2 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 18 | SD_CMD / GPIO4 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 19 | SD_D0 / GPIO6 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 20 | USB3 SSRX− Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 21 | USB3 SSTX− Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 22 | GPIO10 Per interface | Per interface | GPIO10. Check the card implementation for an alternate PWM function. |
| 23 | UART_TX / GPIO8 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 24 | +5 V CPU card supply | CPU card supply | Common chassis and CPU card connection. |
| 25 | BI_DD+ Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 26 | RX+ / BI_DB+ Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 27 | TX+ / BI_DA+ Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 28 | BI_DC+ Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 29 | +5 V CPU card supply | CPU card supply | Common chassis and CPU card connection. |
| 30 | USB1 D+ Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 31 | GND Return | Return | Common chassis and CPU card connection. |
| 32 | EINT0 / GPIO11 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 33 | GND Return | Return | Common chassis and CPU card connection. |
| 34 | USB2 D+ Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 35 | SPI_MOSI / GPIO13 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 36 | B3 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 37 | B5 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 38 | B7 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 39 | SPI_CS / GPIO15 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 40 | G3 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 41 | G5 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 42 | G7 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 43 | POWER# Per interface | Per interface | Active-low power control signal. Follow the chassis and CPU card power sequencing documentation. |
| 44 | R3 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 45 | R5 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 46 | R7 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 47 | LCD_VSYNC Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 48 | LCD_DE Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 49 | I²C_SDA Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 50 | SD_D2 / GPIO1 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 51 | GPIO3 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 52 | SD_CLK / GPIO5 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 53 | SD_D1 / GPIO7 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 54 | USB3 SSRX+ Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 55 | USB3 SSTX+ Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 56 | Ethernet transformer feedback Per interface | Per interface | Feedback connection for the Ethernet transformer circuit. |
| 57 | UART_RX / GPIO9 Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 58 | +5 V CPU card supply | CPU card supply | Common chassis and CPU card connection. |
| 59 | BI_DD− Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 60 | RX− / BI_DB− Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 61 | TX− / BI_DA− Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 62 | BI_DC− Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 63 | +5 V CPU card supply | CPU card supply | Common chassis and CPU card connection. |
| 64 | USB1 D− Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
| 65 | GND Return | Return | Common chassis and CPU card connection. |
| 66 | VREF-TTL Per interface | Per interface | Logic reference for the TTL-level interface. Check the card and chassis design before connecting test equipment. |
| 67 | GND Return | Return | Common chassis and CPU card connection. |
| 68 | USB2 D− Per interface | Per interface | Check the chassis and CPU card implementation for interface support and multiplexing. |
Signal assignments
USB 2.0
Two separate USB 2.0 differential pairs are assigned in the connector.
Electrical limits
| Parameter | Limit | Conditions and source |
|---|---|---|
| Supply from chassis5 V nominal | 5 V nominal | Use a compatible EOMA68 chassis and confirm rail polarity before inserting the card. EOMA-68 Specification v1.0, Table of EOMA-68 Pinouts |
| Chassis identificationI²C address 0x51 | I²C address 0x51 | 7-bit address. The write address byte is 0xA2. EOMA-68 Specification v1.0, I²C |
Models and documents
The map follows the v1.0 table. Check the revision and implemented interfaces on both sides of the connector.
- EOMA68 v1.0
- Published EOMA68 connector assignment.
- EOMA-68 Specification v1.0· Project specification, connector table, I²C and power sequencing.