USB data pair
Keep the D+ and D− polarity consistent at the connector and the bridge. Use the package-specific application circuit for matching and bypass components.
FT232H Hi-Speed USB bridge pinout
The FT232H supports an asynchronous UART, synchronous serial through MPSSE, and parallel FIFO interfaces. It uses a dedicated USB PHY supply and an external clock circuit.
LQFP-48 48 contacts
QFN-48
49 contacts Current packageQFN-48 pinout
QFN-48
27 · ACBUS3
Control or auxiliary I/O. Its assignment depends on the EEPROM settings and active interface mode.
All 49 pins
| Pin | Signal | Direction | Function |
|---|---|---|---|
| 1 | OSCI Input | Input | 12 MHz crystal or external clock input. See §6.3 for crystal and clock requirements. |
| 2 | OSCO Output | Output | 12 MHz crystal oscillator output. |
| 3 | VPHY Supply input | Supply input | USB PHY power. Use the filtered 3.3 V rail in Figure 6.1. |
| 4 | AGND Return | Return | Connect to the ground plane with the other return leads. |
| 5 | REF Analog input | Analog input | USB transceiver current reference. Connect a 12 kΩ, 1% resistor to ground. |
| 6 | DM Bidirectional | Bidirectional | USB D− line. Route with the other data line as a differential pair and use the manufacturer’s reference circuit. |
| 7 | DP Bidirectional | Bidirectional | USB D+ line. Route with the other data line as a differential pair and use the manufacturer’s reference circuit. |
| 8 | VPLL Supply input | Supply input | PLL power. Use the filtered 3.3 V rail in Figure 6.1. |
| 9 | AGND Return | Return | Connect to the ground plane with the other return leads. |
| 10 | GND Return | Return | Connect to the circuit ground plane. |
| 11 | GND Return | Return | Connect to the circuit ground plane. |
| 12 | VCCIO Supply input | Supply input | Sets the UART and configurable pin logic levels. |
| 13 | ADBUS0 Mode dependent | Mode dependent | UART mode assigns TXD. Check the selected mode’s signal table before enabling an external driver. |
| 14 | ADBUS1 Mode dependent | Mode dependent | UART mode assigns RXD. Check the selected mode’s signal table before enabling an external driver. |
| 15 | ADBUS2 Mode dependent | Mode dependent | UART mode assigns RTS#. Check the selected mode’s signal table before enabling an external driver. |
| 16 | ADBUS3 Mode dependent | Mode dependent | UART mode assigns CTS#. Check the selected mode’s signal table before enabling an external driver. |
| 17 | ADBUS4 Mode dependent | Mode dependent | UART mode assigns DTR#. Check the selected mode’s signal table before enabling an external driver. |
| 18 | ADBUS5 Mode dependent | Mode dependent | UART mode assigns DSR#. Check the selected mode’s signal table before enabling an external driver. |
| 19 | ADBUS6 Mode dependent | Mode dependent | UART mode assigns DCD#. Check the selected mode’s signal table before enabling an external driver. |
| 20 | ADBUS7 Mode dependent | Mode dependent | UART mode assigns RI#. Check the selected mode’s signal table before enabling an external driver. |
| 21 | ACBUS0 Mode dependent | Mode dependent | Control or auxiliary I/O. Its assignment depends on the EEPROM settings and active interface mode. |
| 22 | GND Return | Return | Connect to the circuit ground plane. |
| 23 | GND Return | Return | Connect to the circuit ground plane. |
| 24 | VCCIO Supply input | Supply input | Sets the UART and configurable pin logic levels. |
| 25 | ACBUS1 Mode dependent | Mode dependent | Control or auxiliary I/O. Its assignment depends on the EEPROM settings and active interface mode. |
| 26 | ACBUS2 Mode dependent | Mode dependent | Control or auxiliary I/O. Its assignment depends on the EEPROM settings and active interface mode. |
| 27 | ACBUS3 Mode dependent | Mode dependent | Control or auxiliary I/O. Its assignment depends on the EEPROM settings and active interface mode. |
| 28 | ACBUS4 Mode dependent | Mode dependent | Control or auxiliary I/O. Its assignment depends on the EEPROM settings and active interface mode. |
| 29 | ACBUS5 Mode dependent | Mode dependent | Control or auxiliary I/O. Its assignment depends on the EEPROM settings and active interface mode. |
| 30 | ACBUS6 Mode dependent | Mode dependent | Control or auxiliary I/O. Its assignment depends on the EEPROM settings and active interface mode. |
| 31 | ACBUS7 Mode dependent | Mode dependent | Control or auxiliary I/O. Its assignment depends on the EEPROM settings and active interface mode. |
| 32 | ACBUS8 Mode dependent | Mode dependent | Control or auxiliary I/O. Its assignment depends on the EEPROM settings and active interface mode. |
| 33 | ACBUS9 Mode dependent | Mode dependent | Control or auxiliary I/O. Its assignment depends on the EEPROM settings and active interface mode. |
| 34 | RESET# Input | Input | Active-low reset. The internal power-on reset handles a normal bus-powered start. |
| 35 | GND Return | Return | Connect to the circuit ground plane. |
| 36 | GND Return | Return | Connect to the circuit ground plane. |
| 37 | VCCA Regulator output | Regulator output | Internal 1.8 V analog regulator node. Bypass with 100 nF to ground. |
| 38 | VCORE Regulator output | Regulator output | Internal 1.8 V core regulator node. Bypass with 100 nF to ground. |
| 39 | VCCD Regulator input or output | Regulator input or output | In the 5 V configuration this is the 3.3 V output. With a supported 3.3 V supply configuration it is an input. |
| 40 | VREGIN Supply input | Supply input | Input to the internal regulator. In the 5 V configuration, connect to USB VBUS as shown in Figure 6.1. |
| 41 | AGND Return | Return | Connect to the ground plane with the other return leads. |
| 42 | TEST Input | Input | Tie to ground for normal operation. |
| 43 | EEDATA Bidirectional | Bidirectional | Optional EEPROM serial data. See §7.1 for the series and pull-up resistors. |
| 44 | EECLK Output | Output | Optional EEPROM serial clock. High impedance during reset. |
| 45 | EECS Bidirectional | Bidirectional | Optional EEPROM chip select. High impedance during reset. |
| 46 | VCCIO Supply input | Supply input | Sets the UART and configurable pin logic levels. |
| 47 | GND Return | Return | Connect to the circuit ground plane. |
| 48 | GND Return | Return | Connect to the circuit ground plane. |
| EP | EP Floating | Floating | The central solder pad has no internal electrical connection. Follow the package land pattern. |
Signal assignments
Asynchronous UART
Use the receive and transmit pair with a common ground. The signals use logic-level voltages. A separate transceiver is needed for bipolar RS-232.
MPSSE SPI assignment
In MPSSE SPI, ADBUS0 is clock, ADBUS1 is data out, ADBUS2 is data in, and ADBUS3 can act as chip select. The pins start in the configured reset mode, so prevent contention until the host configures MPSSE.
Electrical limits
| Parameter | Limit | Conditions and source |
|---|---|---|
| VCCIO2.97–3.63 V | 2.97–3.63 V | Connect every VCCIO lead. This rail sets the logic output swing. FTDI FT_000288, version 2.2, Table 5.2 |
| VPHY and VPLL3.0–3.6 V | 3.0–3.6 V | Use the supply filter from the FTDI reference circuit. FTDI FT_000288, version 2.2, Table 5.4 |
| VREGIN in the 5 V configuration3.6–5.5 V | 3.6–5.5 V | The separate 3.3 V configuration depends on silicon revision and regulator wiring. FTDI FT_000288, version 2.2, Table 5.2 |
| UART logic thresholds≤ 0.8 V low · ≥ 2.0 V high | ≤ 0.8 V low · ≥ 2.0 V high | LVTTL switching levels at the specified 3.3 V I/O supply. FTDI FT_000288, version 2.2, Table 5.3 |
Models and documents
The two interactive maps cover the FT232HL LQFP-48 and FT232HQ QFN-48. Start with the FTDI reference circuit or the UM232H evaluation module. The companion covers power verification and UART loopback.
- FT232HQ
- FT232HQ · central solder pad
- FTDI FT232H datasheet· FT_000288 v2.2, pin and mode tables, bus-powered circuit in Fig. 6.1, and package drawings.
- FTDI UM232H evaluation module· Assembled FT232H evaluation hardware and module documentation.