Spark Logic

74HC165 connection guide

Wire and test a Texas Instruments SN74HC165 for parallel capture, serial readout or a two-chip chain.

Connect and bypass the supply

With power off, connect the regulated 4.5 V rail to 16 VCC and the supply return to 8 GND. Use a common ground for the host, the register and the test instrument. Fit one 100 nF ceramic capacitor directly across pins 16 and 8 of each chip, close to the package.

4.5 V to pin 16, return to pin 8, 100 nF across both pins on each chip4.5 VReturn100 nF16 VCC8 GND

Complete the signal wiring before power-up. Then measure 4.5 V at pin 16 with the meter common at pin 8. Keep the host outputs from driving the chip while its supply is off.

1 SH/LD 2 CLK 3 E 4 F 5 G 6 H 7 Q̅H 8 GND Used in this circuit
16 VCC Used in this circuit15 CLK INH 14 D 13 C 12 B 11 A 10 SER 9 QH
Top view · Pin 1 at upper left · Schematic outline

Connect the data and control signals

Read two registers on one data line

Jump to the expected result ↓

Use fast CMOS host outputs that swing between GND and the same 4.5 V rail. The receiver on 9 QH must accept that swing. Leave 7 Q̅H open. VCC and GND labels in the signal schematic refer to the same rails as in the power step.

Wire both chips to the same LOAD and CLK outputs. Run U1 pin 9 to U2 pin 10, then run U2 pin 9 to the host input. Fit a separate bypass capacitor at each chip.

U1 pin 9 connects to U2 pin 10. Both chips share host LOAD, host CLK and the supply rails. U2 pin 9 connects to host input.U1 · 74HC165Host LOAD1 SH/LDHost CLK2 CLKGND15 CLK INHVCC11 AGND12 BVCC13 CVCC14 DGND3 EVCC4 FGND5 GGND6 H10 SER9 QHGNDU2 · 74HC165Host LOAD1 SH/LDHost CLK2 CLKGND15 CLK INHGND11 AVCC12 BVCC13 CGND14 DGND3 EVCC4 FVCC5 GVCC6 H10 SER9 QHHost IN
1 SH/LD Used in this circuit2 CLK Used in this circuit3 E Used in this circuit4 F Used in this circuit5 G Used in this circuit6 H Used in this circuit7 Q̅H 8 GND
16 VCC 15 CLK INH Used in this circuit14 D Used in this circuit13 C Used in this circuit12 B Used in this circuit11 A Used in this circuit10 SER Used in this circuit9 QH Used in this circuit
Top view · Pin 1 at upper left · Schematic outline
1 SH/LD Used in this circuit2 CLK Used in this circuit3 E Used in this circuit4 F Used in this circuit5 G Used in this circuit6 H Used in this circuit7 Q̅H 8 GND
16 VCC 15 CLK INH Used in this circuit14 D Used in this circuit13 C Used in this circuit12 B Used in this circuit11 A Used in this circuit10 SER Used in this circuit9 QH Used in this circuit
Top view · Pin 1 at upper left · Schematic outline

U1 9 QH feeds U2 10 SER. U2 QH feeds the host.

Signal wiring for the test pattern

PinConnect to
1 SH/LDHost LOAD
2 CLKHost CLK
15 CLK INHGND
10 SERU1 to GND. U2 from U1 pin 9.
9 QHU1 to U2 pin 10. U2 to host input.
11 A,13 C,14 D,4 FU1 to VCC
12 B,3 E,5 G,6 HU1 to GND
12 B,13 C,4 F,5 G,6 HU2 to VCC
11 A,14 D,3 EU2 to GND

Check the result

  1. Keep 2 CLK LOW and CLK INH grounded. With A–H stable, drive 1 SH/LD LOW for at least 1 µs, then HIGH. Keep the data stable throughout the LOW interval.
  2. Wait at least 1 µs after releasing LOAD. Sample U2 QH first with CLK LOW, then drive CLK HIGH for at least 1 µs and back LOW. Allow at least 1 µs in the LOW phase. Repeat sample-before-pulse until you have 16 samples. You can skip the last pulse.
  3. Probe QH and CLK relative to pin 8. Expect 11100110 00101101 from left to right. The first byte is U2 (H → G → F → E → D → C → B → A), then U1 (H → G → F → E → D → C → B → A).

At 4.5 V TI specifies a settled LOW of at most 0.1 V at 20 µA sink current and a settled HIGH of at least 4.4 V at 20 µA source current. If the sequence is offset by one bit, check the first sample relative to CLK. If you drive CLK INH in another design, raise it only while CLK is HIGH. Raising it while CLK is LOW in shift mode can clock an extra bit.

If the second byte is wrong, probe U1 QH and U2 SER. Verify the jumper and shared CLK and LOAD first. For faster clocks, check the upstream propagation delay, downstream setup and hold, wiring delay and clock skew.

Timing limits and input thresholds

Package and documents

TI package code D · approximately 9.9 × 3.9 mm body · 1.27 mm lead pitch. Use the outline drawing for footprint dimensions and tolerances.

Active order codes
SN74HC165DR, SN74HC165DR.A, SN74HC165DRG3, SN74HC165DRG3.A
Last time buy
SN74HC165DRE4, SN74HC165DRG4, SN74HC165DRG4.A

Package status is from TI's 23 October 2026 addendum, pp. 1–2. Circuit sources: §§5, 6.3, 6.7, 6.10, 6.13, 8.2–8.4, 9.2 Figure 5 and 10.