74HC165 parallel-load shift register
Pinout, timing and operating limits for the Texas Instruments SN74HC165 8-bit parallel-in, serial-out register.
Pinout
15 · CLK INH
HIGH inhibits CLK. Raise only while CLK is HIGH to avoid an extra shift.
Operating range 0 V to VCC, referenced to GND.
All 16 pins
| Pin | Name | Role | Range |
|---|---|---|---|
| 1 | SH/LD | LOW loads A–H asynchronously. HIGH selects shift mode. | 0 V to VCC |
| 2 | CLK | A rising edge shifts when SH/LD is HIGH and CLK INH is LOW. | 0 V to VCC |
| 3 | E | Parallel input to stage E during LOW SH/LD. | 0 V to VCC |
| 4 | F | Parallel input to stage F during LOW SH/LD. | 0 V to VCC |
| 5 | G | Parallel input to stage G during LOW SH/LD. | 0 V to VCC |
| 6 | H | Parallel input to stage H during LOW SH/LD. | 0 V to VCC |
| 7 | Q̅H | Complementary serial output. Leave open if unused. | 0 V to VCC |
| 8 | GND | Supply return and logic reference. | 0 V |
| 9 | QH | Noninverting serial output. Shows H after load, then G through A. | 0 V to VCC |
| 10 | SER | Serial data enters stage A on each shift edge. Tie LOW for zero fill. | 0 V to VCC |
| 11 | A | Parallel input to stage A during LOW SH/LD. | 0 V to VCC |
| 12 | B | Parallel input to stage B during LOW SH/LD. | 0 V to VCC |
| 13 | C | Parallel input to stage C during LOW SH/LD. | 0 V to VCC |
| 14 | D | Parallel input to stage D during LOW SH/LD. | 0 V to VCC |
| 15 | CLK INH | HIGH inhibits CLK. Raise only while CLK is HIGH to avoid an extra shift. | 0 V to VCC |
| 16 | VCC | Positive supply. Bypass to GND close to the package. | 2–6 V |
Pin numbering and functions follow SCLS116H §5, p. 3. The bar in Q̅H marks the complementary output.
Load and shift
Run a valid load after power-up before reading QH. The chip has no dedicated reset pin. Keep all inputs driven or tied to a rail. QH and Q̅H are push-pull outputs.
| Operation | Control signals | Effect |
|---|---|---|
| Parallel load | SH/LD LOW | A–H load independently of CLK, CLK INH and SER. |
| Serial shift | SH/LD HIGH, CLK INH LOW, CLK ↑ | SER enters stage A. The stored bits move one stage toward H. |
| Hold | SH/LD HIGH, no shift edge | The stored word and QH hold. |
On QH, read H → G → F → E → D → C → B → A. H is available after loading and before the first rising clock edge. Read A after seven shifts. The next shift presents the first bit shifted in on SER. Raise CLK INH only with CLK HIGH. A rising CLK INH with CLK LOW also shifts in shift mode.
See SCLS116H §§3, 8.2 and 8.4, pp. 1 and 12–13, or wire a two-chip chain.
Electrical limits
Use VCC 2–6 V and a free-air temperature of −40 to +125 °C. Keep logic voltages between GND and VCC. Fit 100 nF across VCC and GND at each chip.
Digital input thresholds and edge rates
| VCC | LOW max | HIGH min | Δt/ΔV max |
|---|---|---|---|
| 2 V | 0.5 V | 1.5 V | 1000 ns/V |
| 4.5 V | 1.35 V | 3.15 V | 500 ns/V |
| 6 V | 1.8 V | 4.2 V | 400 ns/V |
Use the driver's guaranteed levels at its actual load and the receiver's limits at its actual supply. Check both directions when the host and register use different supplies. TI flags potential double-clocking with slow transitions in the threshold region at 2 V. Use clean, fast edges on the clock inputs.
Digital output levels
| VCC · load magnitude | LOW max | HIGH min |
|---|---|---|
| 4.5 V · 20 µA | 0.1 V | 4.4 V |
| 4.5 V · 4 mA | 0.33 V | 3.7 V |
| 6 V · 5.2 mA | 0.33 V | 5.2 V |
Limits apply over −40 to +125 °C with valid input levels. HIGH sources current and LOW sinks current. The ±25 mA per-output and ±50 mA through VCC or GND values in §6.1 are absolute stress limits.
Timing at 4.5 V
| Timing parameter | Limit |
|---|---|
| SH/LD LOW pulse | 24 ns |
| CLK HIGH and LOW pulse widths (each) | 24 ns |
| SH/LD HIGH before CLK ↑ | 24 ns |
| Parallel data before / after SH/LD ↓ | 30 ns / 5 ns |
| SER before / after CLK ↑ | 12 ns / 5 ns |
| CLK INH LOW before CLK ↑ | 30 ns |
| CLK or SH/LD to QH (50 pF) | 45 ns max |
Times are minimums except where marked. TI specifies a 21 MHz maximum clock at 4.5 V over −40 to +125 °C. Meet both minimum CLK phase widths. In a chain, also budget for clock-to-QH delay, SER setup and hold, and skew. Keep parallel data stable throughout the load pulse.
Source: SCLS116H §§6.1, 6.3, 6.7, 6.10, 6.13 and 10, pp. 4–10 and 15.
Package and documents
TI package code D · approximately 9.9 × 3.9 mm body · 1.27 mm lead pitch. Use the outline drawing for footprint dimensions and tolerances.
- Active order codes
- SN74HC165DR, SN74HC165DR.A, SN74HC165DRG3, SN74HC165DRG3.A
- Last time buy
- SN74HC165DRE4, SN74HC165DRG4, SN74HC165DRG4.A
- TI SNx4HC165 datasheet (PDF)· Texas Instruments SCLS116H, Rev. H (December 2015), package option addendum 23 October 2026
- TI SOIC-16 package outline (PDF)· MPDS178G
- TI SN74HC165 product and ordering information
Package status is from TI's 23 October 2026 addendum, pp. 1–2. Coverage is for the catalog SN74HC165.