Spark Logic

Intel 8051 connection guide

Intel 8051 DIP-40 wiring guide with power, signal assignments, and bench checks.

DIP-40

40 contacts Current package

Intel · Original dual-inline package shown in Intel’s original 8031/8051/8751 specification, Figure 3.

Power and internal code selection

Required

Power VCC from a regulated 5 V supply (±5%). Place a 100 nF ceramic bypass between VCC and VSS. The high strap on EA selects the installed mask ROM at reset address 0000h.

100 nF between VCC rail and GroundVCC rail100 nFGround

Bench checks

  • Confirm the package pin 1 mark before applying power and measure VCC relative to ground at the IC.
  • Use a 100 nF X7R capacitor rated at least 16 V as the local high-frequency bypass. Keep its loop short.
  • Confirm the on-chip mask ROM contains the intended startup code before selecting internal execution.

Intel MCS-51 User’s Manual (1981), pp. 6-1–6-4

Connection scenarios

Apply the HMOS power-on reset

Use Intel’s HMOS power-on circuit for a fast-rising supply. The capacitor couples the VCC rise to RST and the resistor pulls RST to ground as the capacitor charges.

C4 10 µF (+ to VCC) between VCC rail and ResetVCC railC4 10 µF (+ to VCC)Reset
R1 8.2 kΩ between Reset and GroundResetR1 8.2 kΩGround

Bench checks

  • Intel shows 10 µF and 8.2 kΩ and calls for VCC to rise within approximately 10 ms. Use a 10 µF ±20% capacitor rated at least 16 V, positive terminal at VCC if polarized, and an 8.2 kΩ ±5% resistor.
  • The nominal RC product is 82 ms. Verify on the board that RST stays above 3.0 V through oscillator startup and at least 2.18 µs more at 11.0592 MHz. Check cold starts and rapid off/on cycles.
  • At 5.25 V and minimum resistance of 7.79 kΩ, the resistor sees less than 3.6 mW. A 1/8 W part has margin.

Intel MCS-51 Family User’s Manual (1994), chapter 3, p. 3-27, Figure 26, and Intel 1981 p. 6-3

DIP-40 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

Top view. The notch is up, pin 1 is upper left and pin 40 is upper right.
Selected pin details

31 · EA

Input · Control

External Access. Strap HIGH for internal mask ROM at 0000h–0FFFh or LOW for external code from 0000h. The original family drawing uses the EA/VDD label for its EPROM variant.

Intel MCS-51, 1981 pp. 6-1–6-2 and 1994 pp. 3-6–3-7, 3-26–3-27

Electrical limits · Pin in the reference

Models and documents

This map covers the original Intel 8051 in the documented 40-pin DIP. Intel’s 8051AH, 80C51, ROMless 8031 and EPROM 8751 have their own electrical or programming specifications. The early original-device electrical table is marked preliminary.

Intel 8051
Original HMOS device, DIP-40. 4 KiB factory mask ROM, 128 B RAM, 32 port pins, two 16-bit timers, five interrupt sources and a full-duplex serial port.