Spark Logic

Intel 8051 connection guide

Intel 8051 DIP-40 wiring guide with power, signal assignments, and bench checks.

DIP-40

40 contacts Current package

Intel · Original dual-inline package shown in Intel’s original 8031/8051/8751 specification, Figure 3.

Power and internal code selection

Required

Power VCC from a regulated 5 V supply (±5%). Place a 100 nF ceramic bypass between VCC and VSS. The high strap on EA selects the installed mask ROM at reset address 0000h.

100 nF between VCC rail and GroundVCC rail100 nFGround

Bench checks

  • Confirm the package pin 1 mark before applying power and measure VCC relative to ground at the IC.
  • Use a 100 nF X7R capacitor rated at least 16 V as the local high-frequency bypass. Keep its loop short.
  • Confirm the on-chip mask ROM contains the intended startup code before selecting internal execution.

Intel MCS-51 User’s Manual (1981), pp. 6-1–6-4

Connection scenarios

Connect a logic-level UART

Wire RXD and TXD to the opposite UART signals, with a shared ground. Use the logic-level side of a compatible adapter. A conventional RS-232 port requires a transceiver.

Bench checks

  • Verify the adapter delivers HIGH ≥ 2.0 V and LOW ≤ 0.8 V at RXD. Its RXD must accept the MCU’s 2.4 V guaranteed HIGH at no more than 100 µA source load.
  • Set P3.0 and P3.1 latches to 1, use serial mode 1 and match the baud rate, framing and parity at both ends.
  • At 11.0592 MHz, Timer 1 mode 2 with TH1 = TL1 = FDh and SMOD = 0 gives 9600 baud nominal. The calculation is 11.0592 MHz ÷ (12 × 32 × 3).

Intel MCS-51 Family User’s Manual (1994), chapter 3, serial interface section, and Intel 1981 p. 6-3

DIP-40 wiring map

Highlighted contacts are used in the required step or selected circuit. Select a contact to inspect it.

Top view. The notch is up, pin 1 is upper left and pin 40 is upper right.
Selected pin details

1 · P1.0

Bidirectional · Bidirectional

Quasi-bidirectional I/O with internal pull-up. A latch value of 1 releases the pin for input.

After reset · Latch = 1. Pulled HIGH when the pin is unloaded and used as GPIO.

Intel MCS-51, 1981 pp. 6-1–6-2 and 1994 pp. 3-6–3-7, 3-26–3-27

Electrical limits · Pin in the reference

Models and documents

This map covers the original Intel 8051 in the documented 40-pin DIP. Intel’s 8051AH, 80C51, ROMless 8031 and EPROM 8751 have their own electrical or programming specifications. The early original-device electrical table is marked preliminary.

Intel 8051
Original HMOS device, DIP-40. 4 KiB factory mask ROM, 128 B RAM, 32 port pins, two 16-bit timers, five interrupt sources and a full-duplex serial port.